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Layout modification method and system

A layout, modified technology, applied in the field of electronic design automation tools, can solve the problem of high IC cost

Active Publication Date: 2014-02-26
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Costly for IC designers to redesign their ICs using later developed cell designs

Method used

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  • Layout modification method and system
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  • Layout modification method and system

Examples

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Embodiment Construction

[0037] The description of the exemplary embodiments is intended to be read in conjunction with the accompanying drawings, which are considered a part of this entire written description. During description, words such as "lower", "upper", "horizontal", "vertical", "above", "beneath", "upward" , "downward", "top" and "bottom" and their derivatives (for example, "horizontally", "downwardly", "upwardly", etc.) should be understood to refer to the described or the orientation shown in the drawings. These spatially relative positional terms are for convenience of description and do not require that the device be constructed or operated in a particular orientation.

[0038] Methods and systems for modifying IC designs are described below. These methods and systems are suitable for use after design is complete (ie, after offline). Using these techniques, the completed design can be modified to take advantage of the same technology node cell design by adding one or more photomasks w...

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Abstract

The invention provides a method. The method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout. The invention further provides a layout modification method and system.

Description

[0001] This application claims priority to US Provisional Patent Application No. 61 / 655,634, filed June 5, 2012, the entire contents of which are hereby incorporated by reference. technical field [0002] The present invention relates to electronic design automation tools for semiconductor integrated circuit (IC) design and photomask layout generation. Background technique [0003] Semiconductor foundry (foundry) and standard cell library suppliers are continuously improving the design of standard cells and reusable parts. [0004] Modern design processes for integrated circuits are widely used for modular components. Circuit designers typically present design descriptions in register-transfer level (RTL). This RTL source code description (eg, Verilog code) is compiled into instances of "units". A cell is the basic building block of a circuit such as a gate or memory bit cell. A unit implements logic or other electronic functions. Several foundries and independent cell l...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCH01L21/00G06F17/5031G06F17/5081G06F30/3312G06F30/398G06F2111/20G06F2119/06G06F2119/12
Inventor 李孟祥许力中杨士贤余和哲谭竞豪王中兴
Owner TAIWAN SEMICON MFG CO LTD
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