Semiconductor device manufacturing method

Abstract

Provided is a semiconductor device manufacturing method for improving a side wall mask. In the semiconductor device manufacturing method, a barrier layer (2) and a sacrificial layer (3) are formed; by adopting a chemical mechanical polishing (CMP) process, parts of quite different left and right sides on the top portion of a side wall (4) are ground off, and the approximately rectangular part of the bottom portion of the side wall (4) is left and is used as a mask to carry out a subsequent side wall mask technology; in this manner, an undesired result occurring on the subsequent etching due to morphologic asymmetry of the side wall (4) may be reduced as far as possible.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing methods, in particular to a transistor manufacturing method using a sacrificial layer and a barrier layer to improve sidewall transfer technology. Background technique [0002] After semiconductor integrated circuit technology enters the technology node of 90nm feature size, it becomes more and more challenging to maintain or improve transistor performance. In order to continue Moore's Law, the feature size of the device is required to be continuously reduced, but conventional 193nm lithography has basically reached its limit, and other technologies such as EUV and electron beam are still a long time away from commercial application. [0003] Spacer patterning technology, as a low-cost and easy-to-apply lithography technology, is considered to be able to be adopted in the next generation of feature sizes. For details, see the attached figure 1 And attached figure 2 First, a ma...

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Problems solved by technology

[0004] However, the sidewall transfer technology also has obvious shortcomings: the left and right sides of the sidewall morphology are asymmetrical, resulting in different shapes formed by subsequent etching.

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