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A CPU hardware optimization method

An optimization method and hardware technology, applied in the direction of program loading/starting, program control devices, etc., can solve the problems of high bus bandwidth load and low execution efficiency, and achieve the effect of shortening execution time, reducing bandwidth load, and optimizing execution process.

Active Publication Date: 2017-05-17
武汉凌久微电子有限公司
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Problems solved by technology

It can be seen that the execution efficiency of such instructions is low, and the load on the bus bandwidth is high

Method used

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  • A CPU hardware optimization method
  • A CPU hardware optimization method
  • A CPU hardware optimization method

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Embodiment Construction

[0024] 椐 Figure 1 to Figure 5 Shown, a kind of hardware optimization method of CPU, its steps are as follows:

[0025] 1. Configure the burst area through the burst address editor

[0026] Assign values ​​to two general-purpose registers in the CPU so that their values ​​correspond to the lower address and upper address of the burst area. Then set a reserved bit of EFLAG to one, assign these two addresses to the burst configuration register group of the CPU, and then perform a zero-set operation on the reserved bit of EFLAG for the next burst area configuration. Repeat this step multiple times to configure multiple burst regions.

[0027] 2. Accelerate memory-to-memory transfer instructions through hardware optimization

[0028] Taking the REP MOVS instruction as an example, first judge whether the addresses of DS:ESI and ES:EDI are in the burst area through hardware. If it is in the burst area, execute the optimization logic, otherwise execute the original logic. In t...

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Abstract

A hardware optimization method for a CPU comprises the following steps: (1) hardware of a system is designed, wherein the system comprises a master controller, a storage controller, an external bus interface and other modules; (2) a burst region is set, wherein the burst region and a non-burst region in an internal storage can be set simply through a burst address editor; (3) a burst mode is used, wherein the burst mode can be started when the length of data is larger than 32 bits. The hardware optimization method for the CPU has the advantages that the hardware optimization method is completely compatible with an X86 instruction set, and a burst read-write region can be configured entirely to conduct segmented optimization of data read-write; with respect to hardware deign, a peripheral circuit is not added, the number of logic gates of the CPU is rarely increased, and therefore the cost of the system is not affected; the execution time of an instruction is greatly shortened, and the number of bus visit times of the CPU is reduced; the hardware optimization method can be popularized to the CPU design of other CISC or RISC instruction sets, thereby being wide in application range.

Description

technical field [0001] The invention relates to the field of processor hardware design, in particular to the hardware optimization design of CPU (Central Processing Unit) data transmission. Background technique [0002] The data transmission unit has always been an important part of the CPU, and its optimization has always been one of the key points of performance optimization in processor design. The optimization of data transmission component design in domestic processor design is mainly carried out by improving the execution efficiency of Cache (high-speed cache), solving read and write related issues, and adding DMAC (direct memory access controller) components. The execution of data transmission instructions Process optimization is rarely mentioned. Taking the data transmission instruction of the 32-bit X86 instruction set as an example, the execution process is all transmitted one by one from the source address in the traditional one-by-one transmission method. to th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/445
Inventor 朱钟琦曾田阮航王炜
Owner 武汉凌久微电子有限公司
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