Method for manufacturing grid side wall of ONO structure

Abstract

The invention provides a method for manufacturing a grid side wall of an ONO structure. The method comprises the step of forming a first silicon dioxide layer on the two sides and the top of a grid by adopting the furnace tube atomic layer deposition technology, the step of forming a silicon nitride layer on the first silicon dioxide layer by adopting the furnace tube atomic layer deposition technology, and the step of forming a second silicon dioxide layer on the silicon nitride layer by adopting the furnace tube atomic layer deposition technology. The grid side wall of the ONO structure is formed by the second silicon dioxide layer, the silicon nitride layer and the first silicon dioxide layer. According to the method, the evenness and the step covering rate of the grid side wall of the ONO structure are improved, and the performance of an ultimately formed semiconductor device is improved.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to a method for manufacturing gate spacers of an ONO structure. Background technique [0002] In the manufacturing process of the semiconductor process, the gate spacer structure plays an important role in protecting the gate and reducing the short channel effect of the device. ONO (first silicon dioxide layer-silicon nitride layer-second silicon oxide layer) structure is an existing ideal gate spacer structure, please refer to figure 1 The schematic diagram of the gate sidewall structure of the ONO structure shown in the prior art. The gate 11 on the semiconductor substrate 10 is sequentially covered with a first silicon oxide layer 12, a silicon nitride layer 13 and a second silicon nitride layer 14, wherein the silicon nitride layer 13 has a higher density and strength, and can It can effectively prevent the diffusion of water vapor and sodium ions, and is an ideal gate ...

AI Technical Summary

Problems solved by technology

[0003] With the reduction of device line width (55nm and below) and the improvement of integration, traditional furnace tube TEOS (tetraethyl silicate) process or high temperature thermal oxidation (HTO) and furnace tube DCS-NH3 process are used to make ONO structure When the gate spacer is used, the thickness uniformity of the formed gate spacer in the semiconductor substrate and the thickness uniformity between semiconductor substrates are different, and the step coverage on the gate is not ideal, which affects the final The performance of fabricated semiconductor devices

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