Reduce ocd measurement noise with metal via slots

A metal through hole and through hole slot technology, which is used in semiconductor/solid-state device testing/measurement, electrical components, electrical solid-state devices, etc.

Active Publication Date: 2016-06-01
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Thus, while existing methods and structures for performing OCD measurements are generally adequate for their intended purpose, they are not completely satisfactory in every respect

Method used

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  • Reduce ocd measurement noise with metal via slots
  • Reduce ocd measurement noise with metal via slots
  • Reduce ocd measurement noise with metal via slots

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Embodiment Construction

[0030] It is understood that the following disclosure provides many different embodiments, or examples, for implementing various elements of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are of course merely examples and are not intended to be limiting. In addition, the present invention may repeat reference numerals and / or letters in each example. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0031] figure 1 is a flowchart of a method 20 for fabricating a semiconductor device. Method 20 includes block 22, wherein a wafer is provided. A horizontal surface of the wafer on which the interconnect structure is formed is defined by a first horizontal direction and a second horizontal direction. Method 20 includes block 24 wherein a first interconnect layer of an interconnect structure is fo...

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Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches.

Description

technical field [0001] The present invention relates generally to semiconductor device fabrication, and in particular, to structures of interconnect layers and methods of fabrication thereof. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and producing ICs, and thus, similar developments in IC processing and production are required in order to realize these advances. During IC development, functional density (ie, the number of interconnected devices per chip area) has generally increased while geometry size (ie, the smallest component (or line) that can be made using a fabrication process) has decreased. [0003] During IC fabrication, optical critical dimension (OCD) measurements can be ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/528H01L21/768H01L23/544
CPCH01L22/12H01L21/7684H01L22/30H01L23/522H01L2924/0002
Inventor 蔡及铭陈亮光郭涵馨黄富明廖浩任梁明中
Owner TAIWAN SEMICON MFG CO LTD
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