Hierarchical simulation method for three-dimensional chip power supply ground network

Abstract

The invention provides a hierarchical simulation method for a three-dimensional chip power supply ground network. The method comprises the following steps: inputting an original three-dimensional chip power supply ground network; decoupling the original three-dimensional chip power supply ground network so as to divide the original three-dimensional chip power supply ground network into a plurality of independent power supply ground networks with the number as same as the layer number; extracting a port equivalent model of each independent power supply ground network; establishing a new three-dimensional chip power supply ground network according to all the port equivalent models; solving the new three-dimensional chip power supply ground network to obtain port voltage and current of each layer of network; obtaining the internal node voltage of each layer of network according to the port voltage and current of each layer of network. According to the method provided by the invention, simulating calculation can be performed on each layer in parallel, so that the calculating efficiency is improved and the simulating complexity is reduced.

Description

technical field [0001] The invention relates to the technical field of electronic design and automation, in particular to a layered simulation method for a three-dimensional chip power supply network. Background technique [0002] With the advancement of technology, traditional two-dimensional chip design will encounter some bottlenecks, such as increasing on-chip interconnection delay and leakage power consumption. Three-dimensional integrated circuits (3D ICs) stack traditional two-dimensional chips in the vertical direction by introducing Through-Silicon-Via (TSV) through silicon in the vertical direction, which can reduce the length of on-chip interconnection lines , increase the number of I / O ports between chips, and improve data transmission bandwidth. In addition, three-dimensional integrated circuits also have the advantages of supporting heterogeneous integration and smaller external dimensions, and gradually become the development direction of the next generation ...

AI Technical Summary

Problems solved by technology

[0007] In academia, some attention has been paid to the modeling and rapid simulation methods of 3D power and ground networks, such as compact physical model modeling (compact physical model) and frequency domain model dimensionality reduction (Model Order Reduction, MOR). However, These methods regard the power and ground network of the three-dimensional chip as a whole, and the number of unknowns in the established equation set Gx=I is the sum of the power and ground nodes of each layer of chips in the three-dimensional chip, which greatly increases the simulation accuracy. the complexity

[0008] In addition, such as the article Xiang Hu, Thomas Toms, Riko Radojcic, Matt Nowak, Nick Yu and Chung-Kuan Cheng, "Enabling Power Distribution Network Analysis Flows for 3D ICs" 3D Systems Integration Conference (3D IC), 2010IEEE International, pp1-4, As mentioned in 2010, when the chips of each layer of the 3D integrated circuit come from different manufacturers, there will be contradictions between the data sharing requirements between the chips of each layer and the property rights protection requirements of different manufacturers

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