Front-end circuit for analogue-to-digital converter with pipeline structure and time sequence control method for front-end circuit

Abstract

The invention discloses a front-end circuit for an analogue-to-digital converter with a pipeline structure and a time sequence control method for the front-end circuit, and aims to eliminate a sampling and holding amplifier, improve power consumption and noise indexes and reduce conversion delay. The front-end circuit is used for realizing the analogue-to-digital conversion of M1+M2 bits, and acquiring a second analogue residual error signal, wherein the second analogue residual error signal is used for the sampling of the next conversion stage of the front-end circuit in the analogue-to-digital converter with the pipeline structure. The front-end circuit comprises a first conversion stage and a second conversion stage, wherein the first conversion stage is used for directly sampling an input signal to finish the analogue-to-digital conversion of M1 bits, and acquiring a first analogue residual error signal; and the second conversion stage is used for receiving and sampling the first analogue residual error signal to finish the analogue-to-digital conversion of M2 bits, and acquiring the second analogue residual error signal.

Description

Technical field [0001] The present invention generally relates to a front-end circuit of an analog-to-digital converter (ADC), and particularly relates to a front-end circuit of an analog-to-digital converter using a pipeline structure and a timing control method thereof. Background technique [0002] The development of a new generation of electronic systems has put forward higher requirements for the analog-to-digital converter (ADC) as an analog and digital interface, requiring it to have high conversion performance and lower power consumption indicators. The pipeline structure can achieve a better trade-off between speed, accuracy, area and power consumption, and is a structure widely used in high-performance ADC design. A pipelined ADC is usually composed of an input sample-and-hold amplifier (SHA) and a multi-stage pipeline conversion stage (pipeline stage) cascade. Among them, the sample-and-hold amplifier and the first-stage pipeline conversion stage, as the front-end circ...

AI Technical Summary

Problems solved by technology

However, since SHA is at the forefront of A / D conversion in the entire pipeline, its noise and precision requirements are very high, and its existence will cause excessive power consumption (the power consumption of SHA usually accounts for 20%-30% of the entire ADC power consumption. above), noise increase, op amp design difficulty, etc.

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