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Decoupling capacitor and integrated circuit provided with same

A technology of decoupling capacitors and decoupling capacitors, applied in circuits, electrical components, semiconductor devices, etc., can solve problems such as large ESD risks, reduced protection capabilities, gate oxide breakdown, etc., and achieve the effect of enhancing ESD protection characteristics

Active Publication Date: 2013-08-14
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Because the gate oxide of the NMOS transistor is very thin, it can provide a large capacitance, but it is precisely because the gate oxide of the NMOS transistor is very thin that the electrostatic discharge (ESD, Electro-Static discharge) protection capability is reduced, that is, the potential electrostatic discharge risk of breaking down the gate oxide, permanently destroying the chip
With the continuous reduction of process size, especially starting from 90nm process, the gate oxide is getting thinner and thinner. This traditional decoupling capacitor structure is facing more and more ESD risks.

Method used

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  • Decoupling capacitor and integrated circuit provided with same
  • Decoupling capacitor and integrated circuit provided with same
  • Decoupling capacitor and integrated circuit provided with same

Examples

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Embodiment 2

[0034] refer to image 3 , shows a second embodiment of a decoupling capacitor of the present application, including an NMOS transistor 40 and a PMOS transistor 50 . Wherein, the drain (D) of the PMOS transistor 50 is connected to the gate (G) of the NMOS transistor 40 , and the drain (D) of the NMOS transistor 40 is connected to the gate (G) of the PMOS transistor 50 . Wherein, the source (S) voltage of the PMOS transistor is higher than the source (S) voltage of the NMOS transistor. In this application, the gate of the NMOS transistor is connected to the VDD power supply line through the channel resistance of the PMOS transistor (that is, the source of the PMOS transistor is connected to the power supply), and the gate of the PMOS transistor is connected to GND through the channel resistance of the NMOS transistor ( That is, the source of the NMOS transistor is grounded). It is this increased channel resistance that enhances the ESD protection characteristics. It can be u...

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PUM

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Abstract

The application provides a decoupling capacitor, which comprises a decoupling capacitor body and resistor connected with a gate electrode of an MOS transistor, wherein the decoupling capacitor body adopts the MOS transistor. The application further provides a integrated circuit, which comprises the decoupling capacitor comprising an NMOS transistor and a PMOS transistor, wherein a drain of the PMOS transistor is connected onto a gate electrode of the NMOS; a drain of the NMOS transistor is connected onto a gate electrode of the PMOS transistor; and the source voltage of the PMOS transistor is higher than that of the NMOS transistor. The decoupling capacitor and the integrated circuit provided with the decoupling capacitor can increase the ESD protection capability.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, in particular to a decoupling capacitor and an integrated circuit with the decoupling capacitor. Background technique [0002] With the reduction of integrated circuit process geometry, more and more transistors are integrated on a chip, and the clock frequency has been expanded to the range of GHz, the density and speed performance of integrated circuit chips have been significantly improved, making these The switching time of the system composed of devices reaches sub-nanoseconds. However, this high-speed switching process often results in high transient currents, supply voltage variations that cause power supply chatter. At the same time, in order to reduce power consumption, the power supply voltage has been reduced along with the reduction of process size, so integrated circuits will be more and more susceptible to power supply noise. [0003] For this reason, it is c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/94
Inventor 张现聚苏志强丁冲
Owner GIGADEVICE SEMICON (BEIJING) INC
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