A serial communication method of master-slave mii management interface

Abstract

The invention provides a serial communication method for master-slave MII management interfaces. By applying the serial communication method for the master-slave MII management interfaces, a one-drive multiple master-slave control system can smoothly complete MDIO (Management Data Input / Output) data serial communication between MII management interfaces of a master control device and MII management interfaces of a plurality of slave devices under the condition that no MDC (Management Data Clock) clock driving chips offer aids and no MDC signal lines are required, so that data connecting wires between the MII management interfaces of the master control device and the MII management interfaces of the plurality of slave devices are reduced, the reduction of PCB (Printed circuit board) track difficulty of a system is facilitated and the number of PCB layers is reduced; besides, the problem of timing errors of the MDIO data and the MDC clock due to the improper handling of the equal length of the track of MDIO signal lines and the MDC signal lines is also not need to be taken into consideration, so that the PCB track design difficulty of the system is reduced on the whole; and meanwhile the reduction of the usage amount of clock driving chips or the reduction of usage amount of pins of the clock driving chips in the system are facilitated, and the system hardware cost is reduced.

Description

technical field [0001] The invention relates to the fields of computer technology and communication technology, in particular to a serial communication method of a master-slave MII management interface. Background technique [0002] The MII interface (Media Independent Interface, Media Independent Interface) is an Ethernet serial communication standard interface defined by IEEE-802.3. The MII interface provides the interconnection technology between the MAC layer (media access control layer) and the PHY layer (physical layer). The management interface in the MII interface (referred to as MII management interface, also known as SerialManagementInterface, serial management interface) is used to transmit control information and status information between the MAC layer and the PHY layer, and perform MDIO data serial communication through the MII management interface. The MAC layer chip can access the registers of the PHY layer chip, and control and manage the PHY layer chip thro...

AI Technical Summary

Problems solved by technology

It can be seen that since the MII management interface of the MAC layer chip and the PHY layer chip needs to work at the MDC clock frequency, while other modules of the MAC layer chip and the PHY layer chip work at the system clock frequency, the master control device and each slave device except In addition to connecting the system clock driver chip to obtain the system clock (SystmClock, SYSC for short), it is also necessary to connect the MDC clock driver chip to the MII management interface to obtain the MDC clock (MDC for short), or connect the main control device to the MDC clock driver chip to obtain the MDC clock Then transmit the MDC clock to each slave device through the MDC signal line between the MII management interfaces; and because there are many slave devices, there are many connections, which will easily lead to difficulties in system PCB routing and increase in the number of PCB layers. , increasing the difficulty of system PCB routing design; and because there is a requirement for MDIO data and MDC clock timing synchronization between the MII management interface of the master device and the slave device, when routing the PCB, if the MDIO signal line and the MDC signal line are routed Improper handling of line equal lengths may cause MDIO data and MDC clock timing errors due to differences in line transmission delays, which further increases the difficulty of system PCB line design from another level; and the use of multiple clocks in the system is undoubtedly It also increases the usage of the clock driver chip or the pin usage of the clock driver chip in the system, which increases the hardware cost accordingly.

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