Software and hardware synergic simulation verification platform and construction method thereof

Abstract

The invention discloses a software and hardware synergic simulation verification platform and a construction method thereof. The verification platform comprises a testing information acquisition module, a hardware model generation module, a software and hardware interface layer generation module, a first calculation module, a second calculation module and a judgment result output module. The method comprises the steps of obtaining a register transfer level hardware circuit code comprehensively output by a performance function, decompiling the obtained register transfer level hardware circuit code to obtain a hardware model based on SystemC cycle precision, generating a software and hardware interface layer, calling the hardware model through the generated software and hardware interface layer to process testing information, calling the performance function to process the testing information, and judging whether a first calculation processing result is the same as a second calculation processing result. The platform and the method improve simulation verification efficiency of high-level comprehensive design, and can check correctness of a high-level comprehensive tool. The platform and the method are widely applied to system level design.

Description

technical field [0001] The invention relates to digital processing technology, in particular to a software-hardware co-simulation verification platform for high-level integrated hardware circuit design and a construction method thereof. Background technique [0002] Explanation of technical terms: [0003] Binary Decision Diagram: binary decision diagram, referred to as BBD [0004] Boolean Satisfiability Problem: Boolean Satisfiability Problem, referred to as SAT [0005] SystemC: It is a system-level design language that can simultaneously implement high-level software and hardware descriptions [0006] In the design based on register transfer level (RTL), the industry usually uses verification methods based on Binary Decision Diagram (BBD), Boolean Satisfiability Problem (SAT) and other forms to verify RTL and netlist (netlist), RTL and RTL and netlist Equivalence with netlist design to ensure correct design. However, as design complexity and chip capacity increase, r...

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Problems solved by technology

However, as design complexity and chip capacity increase, register-transfer-level design can no longer meet the time-to-market requirements, so system-level design becomes popular and replaces traditional Register Transfer Stage Design

However, there are many insurmountable gaps between the system level design and the register transfer level design, such as the timing difference of the interface, the difference in the internal state of the system level and the register transfer level, and the difference in the operating bit width. Therefore, based on the static state of BDD or SAT The formal verification method is not suitable for the equivalence verification between the register transfer level and the system level design, that is to say, in the system level design, the functional equivalence verification platform between the system level design and the register transfer level design is not Complete

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