Programmable logic array intellectual property (IP) core and system integration method thereof

Abstract

The invention discloses an embedded type programmable logic array intellectual property (IP) core structure which is suitable for programmable system on chip (PSOC) design. The programmable logic array IP core comprises a plurality of programmable logic array block black forms (BLK), an interconnection network, a clock management module direct-current main (DCM), an input-output port and a configuration interface. The invention further discloses a system integration method based on the IP core. Programming is conducted to the programmable logic IP core in a PSOC system through a software system, and the IP core can be configured to a circuit function which needed by users. Reconfigurability of a system can be achieved conveniently by utilizing the flexibility of the IP core and a reconfigurable function, and meanwhile the risks of developing system on a chip (SOC) are reduced.

Description

technical field [0001] The invention belongs to the field of electronic circuit design, and specifically relates to a programmable logic array IP core special structure and a corresponding system integration method. Background technique [0002] System on a Chip (SOC) supported by intellectual property IP (Intellectual Property) core multiplexing and ultra-deep submicron technology has become an important development direction of VLSI. However, SOC design faces many challenges, among which the multiplexing of IP cores is the most critical. The vast majority of SOCs are designed mainly with IP cores, and IP cores have become the fastest growing part of the integrated circuit industry. [0003] The programmable logic array FPGA (Field Programmable Gate Array) was first introduced in the mid-1980s. Because the FPGA has the ability to be reprogrammed (or reconfigurable) in the system, it has brought great strength to the design of a new generation of large-scale integrated circ...

AI Technical Summary

Problems solved by technology

However, the continuous development and upgrading of bus architecture has brought adverse effects on IP core multiplexing and SOC design and implementation

On the one hand, the technical changes or upgrades of the bus may make the previously supported IP cores no longer applicable and need to be modified; on the other hand, it may affect the system-level design of the SOC, and the programmable module has an Processing requires a lot of internal logic resources. At the same time, the pipeline processing method introduced in the bus increases the delay of the data channel, which will affect the efficiency of data transmission.

Images