Chip interconnection structure and chip interconnection method of multi-core network processor

Abstract

The invention discloses a chip interconnection structure and a chip interconnection method of a multi-core network processor. The chip interconnection structure of the multi-core network processor includes that a fast interconnection module, a processing unit and a fast sharing resource are connected with one another through a read-data identify bus, a write identify bus, a write-data identify bus and a command bus, and a slow interconnection module, the processing unit and a slow sharing resource are connected with one another through the read-data identify bus, the write identify bus, the write-data identify bus and the command bus. The chip interconnection method includes the steps of: sending a command, selecting a command, receiving a command, judging whether the command is a read command, sending read-data identify information, selecting the read-data identify information, receiving the read-data identify information, sending write identify information, selecting the write identify information, receiving the write identify information, sending write-data information, selecting the write-data information and receiving the write-data information. The chip interconnection structure and the chip interconnection method is suitable for multi-core network processor, simple in structure, high in bandwidth, and good in parallelism, in expandability and in fairness.

Description

technical field [0001] The invention relates to the field of network devices, and further relates to an on-chip interconnection structure of a multi-core network processor and a method thereof. The invention can make the multi-core network processor provide high bandwidth while having a relatively simple structure, and has good parallelism, expandability and fairness. Background technique [0002] Mainstream network processors generally include several multi-threaded packet processors (PPE), a coprocessor, dynamic random access memory (DRAM) and static random access memory (SRAM) control unit, encryption and decryption unit, network data flow interface unit etc. The coprocessor configures each unit of the network processor when the system is started, and multiple packet processors run in parallel inside the network processor, and control the processing flow through pre-programmed microcode. Data storage and processing units such as storage units (such as DRAM and SRAM unit...

AI Technical Summary

Problems solved by technology

However, the disadvantage of this interconnection structure is that the structure is complex, and it will cost a lot in terms of cost and area.

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