Pinch-off voltage reducing structure of dual-channel high voltage junction field effect transistor (FET) and manufacturing method thereof

Abstract

The invention discloses a pinch-off voltage reducing structure of a dual-channel high voltage junction field effect transistor (FET) and a manufacturing method of the pinch-off voltage reducing structure of the dual-channel high voltage junction FET. A well region provided with a channel region and a drift region is formed in a silicon substrate, a drift region inversion layer is arranged in the drift region, a gate region is formed on the outer side of the channel region, a channel region inversion layer is arranged in the channel region, the transverse width of the channel region inversion layer is longer than the transverse width of the channel region, and two ends of the channel region inversion layer are connected with the gate region. A drain electrode leading-out terminal is formed in the drift region, a source electrode leading-out terminal is formed in the channel region, a gate electrode leading-out terminal is formed in the gate region, and a substrate leading-out terminal is formed in the substrate region. The drift region, the drain electrode leading-out terminal and the source electrode leading-out terminal are in a second conductivity type, the substrate, the drift region inversion layer, the channel region inversion layer, the gate region, the gate leading-out terminal and the substrate leading-out terminal are in a first conductivity type, and electrodes are led out from the leading-out terminals. According to the pinch-off voltage reducing structure of the dual-channel high voltage junction FET and the manufacturing method of the pinch-off voltage reducing structure of the dual-channel high voltage junction FET, impurities which are opposite in type are implanted inside the channel region to form double channels, namely an upper channel and a lower channel, the opposite impurities are arranged in the channel region at the same time, and therefore each channel can be exhausted more easily, and pinch-off voltage is lowered.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a structure for reducing the pinch-off voltage of a double-channel high-voltage junction field effect transistor. The invention also relates to a manufacturing method of the dual-channel high-voltage junction field effect transistor. Background technique [0002] The channel region of the current high-voltage JFET device is an N or P-type single channel, and the pinch-off voltage is relatively high. Such as figure 1 As shown, the channel region of a traditional HV N-channel JFET device is composed of a DNW N-type impurity, and there is only one current channel, which is not easy to be depleted. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide a structure for reducing the pinch-off voltage of a dual-channel high-voltage junction field effect transistor, which can reduce the pinch-off voltage of the jun...

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Problems solved by technology

[0002] The channel region of the current high-voltage JFET device is an N or P-type single channel, and the pinch-off voltage is relatively high.

like figure 1 As shown, the channel region of a traditional HV N-channel JFET device is composed of a DNW N-type impurity, which has only one current channel, which is not easy to be depleted

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