Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Floating-point accumulation/gradual decrease operational method with floating-point precision maintaining function

A floating-point precision and floating-point technology, which is applied in computing, instruments, and electrical digital data processing, can solve problems such as truncation errors, truncation and rounding errors, and achieve the goals of reducing reading, increasing effective digits, and improving performance. Effect

Active Publication Date: 2015-06-24
NAT UNIV OF DEFENSE TECH
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the floating-point addition and subtraction of the prior art, the data exceeding the bit width of the floating-point number will be truncated in the process of order alignment, and a truncation error will be generated in the process
The normalization and rounding processing after the operation will be truncated according to the bit width of the final result, and the mantissa will be processed according to the rounding method, thus truncation or carry will further generate truncation and rounding errors

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Floating-point accumulation/gradual decrease operational method with floating-point precision maintaining function
  • Floating-point accumulation/gradual decrease operational method with floating-point precision maintaining function
  • Floating-point accumulation/gradual decrease operational method with floating-point precision maintaining function

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0023] like image 3 As shown, the implementation steps of the floating-point accumulation / accumulation and subtraction operation method with the function of maintaining floating-point precision in this embodiment are as follows:

[0024] 1) Pre-expand the width of the order register so that the floating-point operation before the floating-point operation does not perform data truncation, expand the width of the result register to store temporary operation results, and expand the width of the binary adder to meet the expanded width. The order register and the extended result register; when performing operations, the floating-point accumulation / subtraction operation is decomposed into the first floating-point addition / subtraction instruction and the subsequent floating-point accumulation / subtraction instruction to obtain the first floating-point The addition / subtraction operation instruction is used as the current operation instruction, and the two operands of the current opera...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a floating-point accumulation / gradual decrease operational method with a floating-point precision maintaining function. The implementation steps are as follows: (1) increasing the widths of a match exponent register, an expansion result register and a binary adder and decomposing the operation into a floating-point addition / subraction operation and a floating-point accumulation / gradual decrease command; (2) executing the floating-point addition / subraction operation, saving the operation result in the expansion result register, normalizing and rounding the operation result, and then writing the operation result into a target floating-point register; and (3) executing the floating-point accumulation / gradual decrease command, during each time of execution of the floating-point accumulation / gradual decrease command, reading the first operand from the floating-point register and the second operand from the expansion result register, then returning to execute the step (2), and after execution of the last floating-point accumulation / gradual decrease command, outputting data in the target floating-point register. The floating-point accumulation / gradual decrease operational method has the advantages of high floating-point precision, easiness in implementing hardware logic, wide range of application and flexibility and convenience in use.

Description

technical field [0001] The invention relates to a functional unit supporting floating-point addition / subtraction operations in a microprocessor system structure, in particular to a floating-point accumulation / subtraction operation method with the function of maintaining floating-point precision. Background technique [0002] Floating point numbers are a way of representing data in a fixed format. Floating point numbers are represented as figure 1 As shown, it specifically includes the sign bit, the floating-point number exponent field, and the floating-point number mantissa field. The sign bit is used to indicate that the data is greater than zero or less than zero; the floating-point number exponent field is used to determine the position of the decimal point of the data; the floating-point number mantissa field is used to represent the valid digits of the data. However, due to the constraints of computer word length and other conditions, floating-point numbers usually ca...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/485
Inventor 倪晓强邰强强窦强王永文张承义高军孙彩霞隋兵才陈微赵天磊黄立波王蕾
Owner NAT UNIV OF DEFENSE TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products