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Resistance random access memory based on vanadium oxide/zinc oxide laminated structure and preparation method thereof

A technology of resistive memory and stacked structure, which is applied in the field of microelectronics to achieve the effect of improving consistency and repeatability

Active Publication Date: 2013-02-06
TIANJIN UNIVERSITY OF TECHNOLOGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In a vanadium oxide film-based resistive memory and its preparation method (CN102130295A), our research group used vanadium oxide as the dielectric layer of the resistive memory to obtain a single-stage resistive memory with a reset current of 40mA , when a single-layer vanadium oxide thin film is used as the material of the resistive switch layer, it has a large reset current; The upper and lower electrodes can obtain unipolar, bipolar, and non-polar RRAM, and the reset current is 10mA, but the consistency and repeatability still need to be improved

Method used

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  • Resistance random access memory based on vanadium oxide/zinc oxide laminated structure and preparation method thereof
  • Resistance random access memory based on vanadium oxide/zinc oxide laminated structure and preparation method thereof
  • Resistance random access memory based on vanadium oxide/zinc oxide laminated structure and preparation method thereof

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Embodiment 1

[0029] A resistive variable memory based on a vanadium oxide / zinc oxide stack structure, such as figure 1 As shown, it is composed of a lower electrode 1, a resistive layer and an upper electrode 4. The resistive layer is a laminated structure composed of a vanadium oxide dielectric layer 2 and a zinc oxide dielectric layer 3. The composition of zinc oxide is ZnO 1-x , where x is 0.1, the thickness of the zinc oxide dielectric layer is 30nm; the composition of vanadium oxide is VO y , wherein y is 0.15, the thickness of the vanadium oxide dielectric layer is 30nm; the lower electrode is Pt, the thickness is 50nm, and the upper electrode is W, the thickness is 50nm.

[0030] The preparation method of the resistive memory, the steps are as follows:

[0031] 1) Si wafers are used as substrates, and SiO is prepared on silicon substrates by thermal oxidation using an oxidation diffusion furnace. 2 Insulation;

[0032] 2) On SiO 2 A 10nm thick Ti adhesion layer was prepared on t...

Embodiment 2

[0040]A resistive variable memory based on a vanadium oxide / zinc oxide laminated structure, the structure is basically the same as that of Embodiment 1, except that W is the lower electrode with a thickness of 50nm, and TiN is the upper electrode with a thickness of 100nm.

[0041] The preparation method of the resistive memory, the steps are as follows:

[0042] 1), 2) are the same as embodiment 1;

[0043] 3) On the Ti adhesion layer, deposit a tungsten lower electrode with a thickness of 50nm by DC magnetron sputtering. The process parameters of DC magnetron sputtering: the target is a φ60mm metal tungsten target, the target intercept is 6.5cm, and the working pressure is 0.5 Pa, Ar flow rate is 20sccm, sputtering power is 50W;

[0044] 4) Deposit a vanadium oxide film with a thickness of 30nm on the lower electrode by radio frequency sputtering. The sputtering process conditions are: the target is a φ60mm vanadium oxide ceramic target, the target intercept is 6.5cm, and t...

Embodiment 3

[0050] A resistive variable memory based on a vanadium oxide / zinc oxide stack structure, the structure is basically the same as that of embodiment 1, the difference is that W is the bottom electrode, W is the top electrode, and the thickness is 50nm.

[0051] The preparation method of the RRAM, the steps and the preparation process of the W electrode are the same as those in Example 1.

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Abstract

The invention relates to a resistance random access memory based on a vanadium oxide / zinc oxide laminated structure, wherein the resistance random access memory is composed of a lower electrode, a resistance random layer and an upper electrode; the resistance random layer is the laminated structure composed of a vanadium oxide medium layer and a zinc oxide medium layer; and films of the vanadium oxide medium layer and the zinc oxide medium layer are prepared by adopting a direct-current sputtering or radio-frequency sputtering method. The resistance random access memory based on the vanadium oxide / zinc oxide laminated structure disclosed by the invention has the advantages that: the resistance random access memory is in the form of the vanadium oxide / zinc oxide laminated structure and has the advantage of controlling double polarity and single polarity of zinc oxide; consistency and repeatability of a device are increased; compared with the single-layer vanadium oxide, reset current is decreased to be below 10 mA; in the bipolar testing process, a progressive reset process exists; different high-impedance resistance can be obtained through reset voltage of different amplitude; at least three resistance values can be obtained; more than ten times of resistance value ratio between every two resistance values exists; therefore, the resistance random access memory based on the vanadium oxide / zinc oxide laminated structure can be applied to multi-value storage.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and in particular relates to a resistive memory based on a vanadium oxide / zinc oxide laminated structure and a preparation method thereof. technical background [0002] Due to its high integration density, fast erasing and writing speed, long retention time, and the potential of multi-value storage, RRAM has attracted extensive attention of researchers in recent years. The research on the resistance switching mechanism, the design of new structures, and the proposal of new materials, researchers are pursuing higher integration density, faster reading and writing speed, and breakthroughs in multi-value storage. [0003] The structure of the resistive variable memory is a simple metal-insulator-metal (MIM) structure, that is, a sandwich structure of upper and lower electrodes and a resistive variable layer in the middle, and most resistive variable layers are a single-layer structure. In ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L45/00G11C13/00
Inventor 张楷亮孙阔王芳陆涛刘凯武长强赵金石
Owner TIANJIN UNIVERSITY OF TECHNOLOGY
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