Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Manufacturing method of MOS (metal oxide semiconductor) transistor

A technology of MOS transistors and manufacturing methods, which is applied in the manufacture of semiconductor/solid-state devices, electrical components, circuits, etc., can solve the problems of insufficiency, low junction capacitance and junction leakage performance, etc., to reduce junction capacitance, reduce junction leakage, control The effect of the short channel effect

Active Publication Date: 2015-05-06
SEMICON MFG INT (SHANGHAI) CORP
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the further reduction of device size requires the formation of shallower ultra-shallow junctions in device manufacturing, and devices have lower junction capacitance and junction leakage performance. The above-mentioned processes have been unable to meet the requirements of device manufacturing.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Manufacturing method of MOS (metal oxide semiconductor) transistor
  • Manufacturing method of MOS (metal oxide semiconductor) transistor
  • Manufacturing method of MOS (metal oxide semiconductor) transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0039] The invention provides a method for manufacturing a MOS transistor, the method comprising the steps of:

[0040] Provide semiconductor substrates;

[0041] forming a gate structure on the semiconductor substrate, the gate structure comprising a gate oxide layer and a polysilicon layer on the gate oxide layer;

[0042] oxidizing sidewalls of the gate structure to form oxide walls;

[0043] using the gate structure and the oxide wall as a mask to remove part of the semiconductor substrate;

[0044] Depositing a dielectric layer on the surface of the semiconductor substrate, the gate structure and the oxide wall;

[0045] Etching the dielectric layer to form sidewalls on both sides of the semiconductor substrate remaining under the gate structure and the oxide wall, the top of the sidewall is lower than the bottom of the gate oxide layer;

[0046] forming a silicon epitaxial layer on the semiconductor substrate from the top to the bottom of the gate oxide layer;

[004...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a manufacturing method of an MOS (metal oxide semiconductor) transistor. A spacer with the top lower than the bottom of a gate oxide is used for inhibiting radial diffusion of a subsequent LDD ( lightly doped source / drain) region subjected to ion implantation, and the depth of a formed subsequent LDD extension region is controlled, so that an obtained ultra-shallow junction is shallower, short-channel effect is reduced, and junction capacitance is lowered; and further, the junction capacitance and the junction leakage are lowered by increasing the charge transfer rate by the aid of a strained silicon layer and a germanium silicon layer.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a MOS transistor. Background technique [0002] As the size of MOSFET devices continues to shrink, especially when entering the node of 65 nanometers and below, MOSFET devices highlight various adverse physical effects due to the extremely short channel, especially the short channel effect (SCE), which makes the device performance and reliability Sexual degradation limits further reduction in size. [0003] Currently, an ultra-shallow junction structure (a doped junction with a junction depth below 100 nm, USJ) is usually used to improve the short-channel effect of the device. Such as figure 1 As shown, in the prior art, after the gate structure 101 is usually formed on the silicon substrate 100, first ions and second ions are used to sequentially perform low-energy lightly doped source / drain region (LDD) ion implantation to form lightly dop...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com