Structure and method of making a dual gate device

Abstract

A first polysilicon (polysilicon-1) is deposited into the deep trenches already formed in the substrate. A first polysilicon polishing process is performed to planarize the exposed surface of polysilicon-1 such that the surface is flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and a second polysilicon (polysilicon-2) is deposited into these shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of polysilicon-2 such that the surface is flush with adjacent surfaces. Then, metal contacts to polysilicon-1 and polysilicon-2 are formed.

Description

[0001] related application [0002] This application claims priority to US Provisional Patent Application Serial No. 61 / 309,824, entitled "Structures and Methods of Fabricating Dual Gate MIS Devices," filed March 2, 2010, which is hereby incorporated by reference in its entirety. Background technique [0003] To save power, it is important to reduce power loss in transistors. In Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices, power loss can be reduced by reducing the device's drain-to-source on-resistance. [0004] To achieve high breakdown voltages in MOS devices, the epitaxial (epi) layer and / or resistivity can be increased, but this can adversely affect on-resistance. To alleviate this problem, a modulated electric field can be introduced perpendicular to the direction of current flow when the device is off. The modulated electric field in the drift region increases the breakdown voltage and allows higher doping concentrations for a given breakdown vol...

AI Technical Summary

Problems solved by technology

The split gate structure offers many advantages, including better switching voltage and breakdown voltage, and lower on-resistance, but this structure is difficult to manufacture

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