Programming control method and device for memory and storage array

Abstract

A programming control method and device for a memory and a memory array, in the memory array, memory cells in the same column share one bit line, memory cells in the same row share one word line, and memory cells in every two rows share one source line; The programming control method includes: applying a word line programming voltage to a word line connected to a target memory cell, applying a 0V voltage to a word line connected to a memory cell sharing a source line with the target memory cell, and applying a word line bias voltage to the remaining word line; applying a source line programming voltage to a source line connected to the target memory cell, applying a source line bias voltage to the remaining source lines; applying a programming current to generate a bit line programming voltage on a bit line connected to the target memory cell, applying The bit line preprograms the voltage to the remaining bit lines. The technical scheme of the invention provides a program control method and device for a memory and a storage array, which reduces the power consumption of the storage array.

Description

technical field [0001] The present invention relates to the technical field of memory, in particular to a programming control method and device for a memory and a memory array. Background technique [0002] Non-volatile memory (NVM, Nonvolatile memory), as an integrated circuit storage device, is widely used in portable computers, mobile phones, etc. , digital music players and other electronic products. Generally, according to the gate structure of the transistors that make up the storage unit, the structure of the non-volatile memory storage unit is divided into two types: stacked gate and split gate structure, in which the split gate storage unit effectively avoids over-erasing effect and has higher programming efficiency and has been widely used. [0003] figure 1 It is a structural diagram of a split-gate memory array, which includes a plurality of memory cells (including memory transistors) arranged in an array, and a plurality of memory cells for selecting the memo...

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Problems solved by technology

[0005] However, for memory cells not to be programmed (referred to simply as non-target memory cells), such as figure 1 For the memory cell d shown, using the prior art programming method will generate a gate-induced drain leakage (GIDL, Gate-Induced Drain Leakage) current, increasing the power consumption of the split-gate memory array

In addition, the bit line pre-programming voltage Vinh is generated from the power supply voltage through the charge pump circuit. When programming the split-gate memory array, the charge pump circuit will also generate power due to the inclusion of power devices (such as resistors, etc.). loss

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