Preparation method of copper interconnecting layer for improving etching appearance and reliability

Abstract

A preparation method of a copper interconnecting layer for improving etching appearance and reliability comprises the following steps: S1: providing a substrate; S2: depositing a functional film system on the substrate; S3: forming a first etching window; S4: forming a second etching window; S5: etching to form a groove communicated with the substrate; S6: depositing a copper barrier layer and a copper seed layer in the groove, and forming a copper filling and depositing layer; and S7: forming a copper interconnecting layer through chemical mechanical polishing. An etched pattern prepared by the preparation method of the copper interconnecting layer for improving the etching appearance and the reliability does not have an obvious jump; a side cutting phenomenon of a transitional interface of an ultralow dielectric constant film and a low dielectric constant film is not obvious; and the covering quality of the copper barrier layer and the copper seed layer of the copper interconnecting layer prepared by the preparation method of the copper interconnecting layer for improving the etching appearance and the reliability is improved, thus further improving the reliability of a semiconductor device.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a copper interconnect preparation method for improving etching morphology and improving reliability. Background technique [0002] With the continuous advancement of VLSI process technology, the feature size of semiconductor devices continues to shrink, and the chip area continues to increase. We are faced with the problem of how to overcome the significant increase in RC delay caused by the rapid increase in connection length. In particular, due to the increasing influence of the capacitance between metal wiring lines, the performance of the device is greatly reduced, which has become a key restrictive factor for the further development of the semiconductor industry. [0003] In order to reduce the RC delay caused by interconnection, various measures have been adopted. One of these is the use of ultra-low-k (Ultra-low-k) materials to reduce parasitic capacitance b...

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Problems solved by technology

[0015] The present invention is aimed at the prior art, where the ultra-low dielectric constant film under the ultra-low dielectric constant protective layer is bow-shaped by adopting the traditional method, and the transition interface of the material will have obvious severe Defects in the process such as side cuts provide a copper interconnection preparation method that improves etching morphology and improves reliability

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