Chip with electrostatic protection function

Abstract

The invention relates to an integrated circuit and discloses a chip with a static protecting function. According to the chip, in an ambient environment of a static protecting module, P+GUARD RINGs on the left side and the right side of the chip are removed and P+GUARD RINGs on the upper side and the lower side of the chip are retained. After the P+GUARD RINGs on the left side and the right side of the chip are removed, the P+GUARD RINGs seen from any one finger in the static protecting module are completely identical, so that the resistance between the finger of each MOS (Metal Oxide Semiconductor) tube in the static protecting module and the P+GUARD RINGs tends to be consistent, and further the conducting capacity of each finger in the static protecting module tends to be consistent, the MOS tubes can be uniformly conducted and the static protecting performance of the chip under the condition that the area is not increased is ensured.

Description

technical field [0001] The invention relates to an integrated circuit, in particular to a technology for improving the electrostatic protection performance of a chip. Background technique [0002] In order to prevent the chip from being damaged by static electricity from the pins and damage the internal circuit of the chip, when designing the chip, an electrostatic protection module composed of multiple metal-oxide-semiconductor (MOS) tubes is usually designed inside the chip to improve the performance of the chip. electrostatic protection performance. In order to reduce the area of ​​the electrostatic protection module as much as possible, a commonly used circuit of the electrostatic protection module connected to the pressure pad (PAD) is as follows: figure 1 As shown, the corresponding layout structure is as follows figure 2 shown. [0003] figure 1 The cross-sectional view of the ESD protection module connected to the commonly used PAD is shown in image 3 As shown...

AI Technical Summary

Problems solved by technology

It can be seen that the performance of the above two improvement schemes is not ideal in practical applications.

[0008] The inventors of the present invention have found that a ring of substrate connections around the ESD protection module will affect the conduction capability of the fingers. If the fingers in the ESD protection module cannot truly achieve uniform conduction, the ESD protection performance of the chip will be affected. have an impact, therefore, although the figure 1 , figure 2 The ESD protection module shown has a reduced area, but the ESD protection performance of the chip cannot be guaranteed, and no better solution has been proposed in the prior art

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