FPGA task scheduling method based on condition preemption

Abstract

The invention relates to an FPGA (Field Programmable Gate Array) task scheduling method based on condition preemption. The FPGA task scheduling method comprises the following specific steps: firstly, establishing a waiting queue for placing a task waited to enter an FPGA; secondly, setting the time entering the FPGA by a first task in the wait queue as a first appointment time; thirdly, sequentially acquiring non-first tasks and acquiring the execution time of the non-first tasks; fourthly, judging whether the non-first tasks meet the preemption conditions, i.e., the current time and the task execution time is not more than the first appointment time of the first task of the wait queue, if the preemption conditions are met, turning into the fifth step and otherwise, turning into the seventh step; fifthly, judging whether enough free space in the FPGA at the time is allowed to place the task or not, if so, turning into the sixth step and otherwise, turning into the seventh step; sixthly, placing the task into the FPGA for executing prior to the first task in the wait queue; and seventhly, enabling the task to continue waiting. According to the FPGA task scheduling method, the sequence of the tasks entering the FPGA for executing in the wait queue is adjusted, so that the task can be placed in the FPGA for executing prior to the first-come task and further the waiting time of the task is shortened and the execution efficiency of the task is effectively increased.

Description

technical field [0001] The invention relates to an FPGA task scheduling method based on conditional preemption. Background technique [0002] The reconfigurable space and tasks inside the FPGA are both two-dimensional rectangles. There are no strict restrictions on the location selection of the task in the FPGA. As long as there is a blank block in the FPGA that is larger than the logical block area required by the task, the task can be placed in the FPGA to run. Assume that a batch of task queues with no data correlation among them arrive at the reconfigurable component FPGA sequentially. At this time, it is necessary to adjust the order of tasks entering the FPGA according to the resource occupancy of the FPGA, and at the same time, design the algorithm in a reasonable two-dimensional space. place tasks. By comparing the total time spent executing the task set, the probability that the task can enter the FPGA in time to be executed after the task arrives at the FPGA, and...

AI Technical Summary

Problems solved by technology

The disadvantage of this method is that it is necessary to use a matrix to represent the usage of the FPGA, and use the matrix elements to record information such as the departure time of the task, and all matrix element information must be updated at each moment, which has high complexity.

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