Interrupt control method for Feiteng server

Abstract

The invention discloses an interrupt control method for a Feiteng server, comprising the following steps: initialization; a hardware interrupt source generates a corresponding type of interrupt signal through a hardware control logic component in the South Bridge CS5536, and an interrupt controller in the South Bridge CS5536 The 8259A routing output is a public interrupt trigger signal, and the corresponding interrupt bit is modified in the internal register of the interrupt controller 8259A. The public interrupt trigger signal is converted into an interrupt message message by the bridge chip mapping and transmitted to the PCIE bus; The PCIE bus obtains the interrupt message message, enters the interrupt state and calls a common interrupt response function, reads the internal register of the interrupt controller 8259A to obtain the interrupt bit, thereby determining the hardware interrupt source and processing the interrupt. The invention enables the Feiteng processor to receive the interruption message message of the CS5536 device in real time, respond accurately and in real time, and process various interruptions.

Description

technical field [0001] The invention relates to the technical field of operating system interruption, in particular to an interruption control method for a Feiteng server. Background technique [0002] The Phytium server adopts two Phytium processors, each processor is composed of 8 cores and 64 hard threads, and the processor frequency is 800MHz~1GHz. It provides 6 PCIE2.0 bus slots through point-to-point high-speed switching chips, and the highest single The IO frequency can reach 5Gbps. [0003] Feiteng server adopts PCI bus standard Southbridge CS5536, which integrates hardware interface control logic such as USB controller, IDE disk controller, audio controller, RTC real-time clock and keyboard and mouse PS / 2 interface controller. The monolithic 8259A includes 8 interrupt input pins, 1 interrupt output pin, 1 interrupt acknowledge pin, cascade pin and other control pins. Through cascading pins, multiple 8259As can be connected in series in a "master-slave" configurati...

AI Technical Summary

Problems solved by technology

There are two typical 8259A application methods: one is to use an independent 8259A chip to control the interrupt, and the peripheral device interrupt is directly input to the 8259A, and then passed to the processor through the interrupt output pin of the 8259A for interrupt processing; the other is to integrate In the application of 8259A in South Bridge CS5536, the device interrupt supported by CS5536 chip is directly processed through this interrupt controller. This integrated design method is generally only used on X86 series processor platforms, and has X86 architecture dependence.

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