Layout and schematic diagram consistency comparison method for multi-voltage chip design

Abstract

The invention discloses a layout and schematic diagram consistency comparison method for multi-voltage chip design, which comprises the steps of: amending a script file of a layout netlist and executing the script file to amend the layout netlist. The procedure of amending the script file comprises the steps of: finding the power supply port titles and subject power supply domains of functional modules of a chip; respectively adding modules corresponding to the power supply port titles and power supply ports of standard units in the layout netlist; adding the power supply connecting line titles in the layout netlist according to the subject power supply domains of the functional modules; and adding the power supply connecting line titles of all functional modules in the top layer of the layout netlist. The method of the invention has the advantages of improving the check efficiency and reliability, reducing the check risk and saving the design cost.

Description

technical field [0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to the layout and principle of a multi-voltage chip design Figure 1 consistency comparison method. Background technique [0002] In the existing chip design, the layout and principle must be carried out after the chip layout design is completed. Figure 1 Consistency comparison (Layout versus Schematic, LVS) to ensure the consistency of layout and circuit schematic. Such as figure 1 As shown, it is the flow chart of the existing LVS, the steps of the existing LVS include the steps of extracting the layout netlist (Layout Netlist) from the layout database (Layout Database), and performing the comparison under the environment of the LVS design rule run set (Runset) A step of performing a consistency comparison (Compare) between the layout netlist and the schematic netlist (Schematic Netlist). The layout netlist can also be modified through a la...

AI Technical Summary

Problems solved by technology

[0004] The first method is to modify the runset. In the runset, multiple power pins of low-power related cells are forcibly defined as one power supply, so that LVS can succeed, but this method will bring certain risks, causing LVS to fail to reflect the real situation.

[0005] The second method is to modify and connect multiple power supplies of low-power-related cells into one power supply in the layout, and then change back to the original connection in the layout after the LVS test is successful. This is not only cumbersome, time-consuming and labor-intensive, but also It will bring certain risks, causing LVS to fail to reflect the real situation

[0006] Therefore, for the existing multi-voltage chip design, the efficiency of LVS in the existing technology is relatively low, and there are certain risks.

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