Method for generating nickel alloy self-aligned silicide

Abstract

The invention discloses a method for generating a nickel alloy self-aligned silicide, comprising the following steps of: providing to-be-produced wafers; selecting a first wafer and a second wafer from the to-be-produced wafers; generating a first nickel alloy metal film on the surface of the first wafer by a first nickel alloy target; generating a first nickel alloy self-aligned silicide on the first wafer by the first nickel alloy metal film; looking up the defect area on the first wafer; producing a second nickel alloy target; generating a second nickel alloy metal film on the surface of the second wafer by the second nickel alloy target; and generating a second nickel alloy self-aligned silicide on the second wafer by the second nickel alloy metal film. The erosion action on the channel region of a CMOS (complementary metal oxide semiconductor) apparatus by nickel in the nickel alloy self-aligned silicide can be efficiently reduced, the performance of the CMOS apparatus can be improved, and the yield of the wafer can be increased according to the method for generating the nickel alloy self-aligned silicide disclosed by the invention. The dosages of expensive constrained metals are efficiently reduced while the performance of the CMOS apparatus is improved via the method for generating the nickel alloy self-aligned silicide disclosed by the invention.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to a method for generating nickel alloy self-aligned silicide. Background technique [0002] In the semiconductor manufacturing process, the complementary metal oxide semiconductor (CMOS) device formed on the wafer is composed of a metal gate region, a silicon oxide gate dielectric region and a semiconductor silicon substrate. Wherein, the gate region is mostly made of polysilicon. However, the use of polysilicon leads to other problems, such as the degradation of device performance due to the high resistance of polysilicon. Therefore, the currently adopted method is to perform a silicide process after the device is formed to form a layer of metal silicide on the gate region and the source / drain region, thereby reducing the resistance of the device. [0003] The process of forming a layer of metal silicide on the gate region and source / drain region of a CMOS device is calle...

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Problems solved by technology

[0010] In order to solve the problem that the prior art cannot effectively and economically reduce the corrosion effect of nickel in the nickel alloy salicide layer on the channel region of a CMOS device, the present invention provides a method for generating nickel alloy salicide method, said method comprising the following steps:

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