Wafer-level columnar bump packaging structure

A technology of column bumps and packaging structure, applied in electrical components, electric solid devices, circuits, etc., can solve the problems of affecting soldering quality, performance and reliability of solder bumps, etc., to increase the number of functional output ports, meet the density The effect of spacing

Inactive Publication Date: 2012-05-02
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In the wafer-level packaging process formed by the prior art, since the solder bump material directly contacts the metal wetting layer, the copper in the metal wetting layer easily diffuses into the tin of the solder bump to form a copper-tin alloy, which affects the soldering quality
At the same time, before the solder is formed on the metal wetting layer, the exposed wetting layer is easily oxidized, which reduces the performance and reliability of the subsequently formed solder bumps

Method used

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  • Wafer-level columnar bump packaging structure
  • Wafer-level columnar bump packaging structure
  • Wafer-level columnar bump packaging structure

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Embodiment Construction

[0024] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0025] figure 2 It is a schematic diagram of a wafer-level stud bump packaging structure of the present invention, and the packaging structure includes: a chip 300, a connection layer and a solder bump 308b; the upper surface of the chip 300 is provided with a pad 301 and a passivation layer 302, so The passivation layer 302 covers the upper surface of the chip 300 other than the pad 301; the bottom of the connection layer is placed on the pad 301 of the chip 300, and the top of the connection layer is provided with a solder bump 308b; Including heat-resistant metal layer 303, metal wetting layer 304, adhesion layer 306 and barrier layer 307 in sequence; the material of the heat-resistant metal layer 303 is titanium, chromium, tantalum or their combination; the metal wetting layer 304 The material is copper, aluminum, nickel or a combina...

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Abstract

The invention discloses a wafer-level columnar bump packaging structure which comprises a chip, a connection layer and a solder bump, wherein the upper surface of the chip is provided with a bonding pad and a passivation layer; the passivation layer is covered on the upper surface, except for the bonding pad, of the chip; the bottom of the connection layer is arranged on the bonding pad of the chip; the top of the connection layer is provided with the solder bump; the connection layer comprises a heat-resisting metal layer, a metal wetting layer, an adhesion layer and a blocking layer sequentially from bottom to top; and the adhesion layer is made of copper, and the blocking layer is made of nickel. According to the invention, the electric property and reliability of the wafer-level columnar bump packaging structure are improved, and the structure is suitable for wafer-level packaging with fine pitches for the bonding pad and multiple output functions.

Description

technical field [0001] The invention relates to the field of semiconductor device packaging, in particular to a packaging structure of a wafer level chip scale package (Wafer Levelchip Scale Package, WLCSP). Background technique [0002] In recent years, since the microcircuit manufacturing of chips is developing toward high integration, the chip packaging also needs to develop in the direction of high power, high density, thinness and miniaturization. Chip packaging means that after the chip is manufactured, the chip is wrapped in plastic or ceramic materials to protect the chip from external moisture and mechanical damage. The main functions of the chip package are power distribution, signal distribution, heat dissipation and protection support. [0003] Since today's electronic products are required to be light, thin, small and highly integrated, the fabrication of integrated circuits will be miniaturized, resulting in an increase in the number of logic circuits containe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/488H01L23/00
CPCH01L2224/0361H01L2224/03912H01L2224/1147
Inventor 丁万春
Owner NANTONG FUJITSU MICROELECTRONICS
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