Welding disc and silicon-on-insulator (SOI) device with same

Abstract

The invention discloses a welding disc, which comprises a plurality of welding disc metal layers, wherein the welding disc metal layers close to a semiconductor gasket and a semiconductor substrate form a parasitic capacitor; and the welding disc metal layers close to the semiconductor substrate are partitioned into parts which are separated from one another to reduce the opposite area of two pole plates of the parasitic capacitor, so that a parasitic capacitance value is reduced. The invention also discloses a silicon-on-insulator (SOI) device. The device comprises the welding disc, wherein a conductive layer which is used as a shielding layer is arranged inside the welding disc, so that a non-linear changeable parasitic capacitor inside an integrated circuit is changed into a constant parasitic capacitor; further, a shallow trench isolation (STI) area with increased depth is arranged inside the SOI device, so that the parasitic capacitance value is reduced. When the SOI device is operated, a radio frequency signal applied onto the device can be leaked out of the parasitic capacitor as few as possible; and the acquired radio frequency signal is a linear signal and meets the using requirement of radio frequency equipment.

Description

technical field [0001] The invention relates to a pad of a semiconductor integrated circuit, in particular to a pad in a radio frequency manufacturing process; the invention also relates to a silicon-on-insulator device with the pad. Background technique [0002] In the field of semiconductor manufacturing, after the integrated circuit is manufactured, a pad is usually formed above the interconnection structure layer, and the pad is electrically connected to the internal circuit as an interface between the internal circuit and the external signal circuit. [0003] At the same time, as the feature size of the chip continues to decrease, the speed of the chip is required to be faster and faster, and the requirements for the parasitic capacitance formed inside various semiconductor devices are getting higher and higher. The smaller the parasitic capacitance, the better the running speed and frequency characteristics of the chip, and the less signal leakage from the parasitic ca...

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Problems solved by technology

[0006] Through research, it is found that the above-mentioned pad structure that can reduce parasitic capacitance has obvious disadvantages: the formation of shallow trench isolation layer needs chemical mechanical planarization (CMP) process to complete, because CMP has a castellation (Disshing) effect, it is generally not easy Realize the formation of a shallow trench isolation layer in the area directly below the pad metal layer; in addition, the characteristics of the preparation process of the shallow trench isolation layer determine that the height of the shallow trench isolation layer (depth in the Z direction) is limited, which will limit the upper and lower poles. The expansion of the spacing between the boards further limits the effect of reducing the parasitic capacitance

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