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Multiple input-multiple clock maintenance obstruction type JK trigger

A multi-input, blocking technology, applied in the electronic field, can solve problems such as inconvenient design, clock load current, power consumption, electromagnetic radiation interference, etc., and achieve the effect of fast storage speed and simple data selection circuit

Inactive Publication Date: 2012-02-15
JIANGSU UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

With the continuous improvement of integrated circuit integration, the contradictions caused by this method, such as clock offset, clock load current, power consumption, electromagnetic radiation interference, etc., are prominent, and event-driven distributed systems and asynchronous circuits have overcome the synchronous The above shortcomings of the circuit, but the existing flip-flops are not convenient for the design of event-driven distributed systems and asynchronous circuits

Method used

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  • Multiple input-multiple clock maintenance obstruction type JK trigger
  • Multiple input-multiple clock maintenance obstruction type JK trigger
  • Multiple input-multiple clock maintenance obstruction type JK trigger

Examples

Experimental program
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Embodiment Construction

[0017] figure 1 It is an embodiment of the present invention, a circuit schematic diagram of a 3-input-3 clock maintaining blocking JK flip-flop, the flip-flop has three sets of data inputs (j1, k1), (j2, k2), (j3, k3), corresponding The three clocks are cp1, cp2, and cp3 respectively, and the output terminals are q and nq, and nq and q are logically complementary.

[0018] The 3-input-3 clock maintaining blocking JK flip-flop includes a multi-input basic RS latch, 3 input units and 3 JK conversion circuits. Wherein the NAND gates I20, I21, I22, I25 form the first input unit, the NAND gates I17, I18, I19, I24 form the second input unit, and the NAND gates I14, I15, I16, I23 form the third input unit; or Gate I30, AND gate I35, I36 and NAND gate I38 form the first JK conversion circuit, OR gate I29, AND gate I33, I34 and NAND gate I37 form the second JK conversion circuit, OR gate I28, AND gate I31, I32 The NAND gate I39 forms the third JK conversion circuit.

[0019] The ou...

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Abstract

The invention discloses a multiple input-multiple clock maintenance obstruction type JK trigger which comprises a multiple input basic RS latch register, two or more input units and JK converting circuits. Two output terminals of the multiple input basic latch register are q and nq respectively. Quantities of the input units and the JK converting circuits are same. Two output terminals of any input unit are connected to an input terminal of the multiple input basic latch register respectively to form a maintenance obstruction type D trigger. The input units comprise data input terminals and clock trigger ends. The data input terminals of the input units connect with output terminals of the JK converting circuits. The JK converting circuits have two data input terminals. The multiple input-multiple clock maintenance obstruction type JK trigger can be used as a common memory, and can be applied to design of a sequential circuit, especially design of a distributed system and an asynchronous circuit of event driven. Compared with a present trigger, according to the multiple input-multiple clock maintenance obstruction type JK trigger, in the case of multipath data input, direct event driving is employed, a data selection circuit is simple, and a storing speed is rapid.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a flip-flop circuit, in particular to a maintenance blocking JK flip-flop with multiple data input channels and multiple clock terminals and a circuit with trigger priority. Background technique [0002] Flip-flop is a device with storage function, which is used to form various sequential logic circuits in digital electronic technology. There are many types of flip-flops: according to the trigger mode, it is divided into level trigger, master-slave trigger, and edge trigger; according to the logic function, it is divided into RS flip-flop, D flip-flop, JK flip-flop, T flip-flop, etc. The characteristics of the trigger are described by the trigger mode and logic function. The trigger mode is used to determine the characteristics of the state change, that is, the way to receive the input signal to change the state; the logic function determines the direction of the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/02
Inventor 赵不贿
Owner JIANGSU UNIV
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