Method and device for realizing instruction cache path selection in superscaler processor

Abstract

The invention discloses a method and a device for realizing instruction cache path selection in a superscaler processor, wherein the method comprises the following steps of: judging a fetch mode at least according to an instruction fetch request, performing path prediction with a path history mode according to fetch mode attributed to sequence fetch scenes, and performing path prediction with a path prediction mode according to the fetch mode attributed to non-sequence fetch scenes. Therefore, the energy efficiency of the superscaler processor is integrally increased; and the overall energy consumption of the superscaler processor is reduced as a large amount of unnecessary path Tag comparisons and Data access are not needed and less extra resources are used.

Description

technical field [0001] The invention relates to the design of a modern microprocessor and its application system, in particular to a method and a device for realizing instruction cache way selection by a superscalar processor. Background technique [0002] The design of current processors no longer takes performance or energy consumption as the sole goal, but comprehensively considers the two design elements, with high energy efficiency as the main design goal. In order to fully explore the instruction-level parallelism of superscalar processors, there are high requirements for the instruction fetch bandwidth and instruction fetch delay of the processor's instruction cache (ICache, Instruction Cache). Provide multiple instructions without interruption. However, the set associative structure of the instruction cache (that is, the instruction cache uses multiple way structures to store instructions) often causes a large amount of non-hit way energy consumption loss. Therefor...

AI Technical Summary

Problems solved by technology

[0009] Second, for the unique non-aligned instruction fetch situation in superscalar processors (special order inter-line instruction fetch situation, figure 1 indicated by the solid arrow in the center), the existing path selection methods have not been able to solve it well

The existing way history method only reads the way pointer to predict the way where the next instruction is fetched only when the last instruction of the Cache line is fetched, so it is impossible to read two parts of instructions at the same time (that is, two consecutive addresses instructions in the Cache line)

However, the existing way prediction method may also cause the latter part of the above two parts of instructions to be unable to be read due to prediction errors.

[0010] Third, in the case of non-sequential fetching, the update mechanism of the way history technology is relatively complicated, which will lead to the problem of suspension of fetching and loss of useful way pointers

[0014] Since the existing way history methods are only discussed and tested for single-issue processors, it is assumed that the update operation of the way pointer can be ignored when ICache has row replacement; The selection process uses a combination of way prediction and way history for the fetch mode, so the advantages of both are not fully utilized

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