Time-interleaved split ADC (Analog-to-Digital Converter) calibration structure without redundant channel and adaptive calibration method thereof

Abstract

The invention discloses a time-interleaved split ADC (Analog-to-Digital Converter) calibration structure without a redundant channel and an adaptive calibration method thereof. The time-interleaved split ADC calibration structure is characterized in that: a time-interleaved ADC sub-module (sub TIADC-A) with sampling rate fs consisting of N split ADC channels with sampling rate fs / N and a time-interleaved ADC sub-module (sub TIADC-B) with sampling rate fs consisting of L split ADC channels with sampling rate of fs / L together form a split channel mutual calibration-based master TIADC. The same input signal is sampled and converted by the sub TIADC-A and the sub TIADC-B at the same sampling rate fs on the same moment; and difference converted and output by the sub TIADC-A and the sub TIADC-B is used in a zero approaching adaptive calibration algorithm to calculate a mismatch error estimation value among split ADC channels. When the mismatch error among the channels is correctly calibrated, the arithmetic mean value of the converted and output values of the sub TIADC-A and the sub TIADC-B is used as the final converted and output value of the split channel mutual calibration-based master TIADC. The calibration structure and the calibration method are low in computation complexity, easy in hardware implementation and can be applied to TIADC calibration with any number of channels.

Description

technical field [0001] The invention relates to the technical field of high-speed and high-precision analog-to-digital conversion, in particular to a structure and method for calibrating mismatch errors between channels in a time-interleaved ADC. Background technique [0002] Modern electronic systems such as communication systems, radar, and image / video processing require high-speed, high-precision analog-to-digital converters (ADCs). Traditional single-channel analog-to-digital converters, such as pipelined ADCs, will face physical limitations in achieving high speed while maintaining high precision, especially as deep submicron CMOS processes move to lower power supply voltages and smaller feature sizes The direction of development will make the design of high-precision, high-speed ADCs using traditional structures more difficult. An effective solution is to break through the limitation brought by process factors through multi-channel time crossover technology, so as to ...

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Problems solved by technology

John A.McNeill and Christopher David et al. proposed a TIADC that uses 2M+1 split ADC channels (Split ADC) intercalibration method to achieve M-fold rate improvement (the channel sampling rate in the system is fs / M, and the system rate is fs ) Adaptive Calibration for All-Digital Correction of Time-Interleaved ADC Errors[J].IEEE Transactions on circuits and systems-II: Express Briefs, vol.56, no.5, pp.344-348, 2009.), but this method must design a redundant split ADC channel to assist in the completion of calibration

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