An Automatic Test Vector Generation Method Based on Generalized Folding Sets

Abstract

An automatic test vector generation method based on a general folding set comprises the following steps of: firstly, classifying faults into faults easy to test and faults difficult to test through random tests, merging the faults difficult to test, dividing the number of the faults difficult to test which can be tested by using the same test vector into groups, selecting two groups of faults having the maximal number of faults capable of being merged together, judging an original input of producing influence during the rollback process to each signal by employing the influence range technology, directing the generation process of the test vectors to generate two corresponding test vectors, determining the corresponding general folding set by the two test vectors, performing fault simulation by using each test vector of the general folding set, and checking all the faults which can be tested by the general folding set; next, generating complete general folding sets for the left faults by the method until all the faults can be completely detected; and finally obtaining a plurality of determined general folding sets. The method provided by the invention has the advantages that test data can be compressed according to a general folding principle, that is to say, the generated data is easier to compress.

Description

【Technical field】 [0001] The invention relates to an integrated circuit testing method, in particular to an automatic testing vector generation method. 【Background technique】 [0002] Since the establishment of the integrated circuit industry, how to test integrated circuits in the most economical and fastest way and obtain good test quality has always been a very important issue. With the continuous development of integrated circuit manufacturing technology, the scale and complexity of integrated circuits are increasing day by day, making its testing more and more difficult, and the proportion of testing cost in the total cost is constantly increasing. Testing has become a bottleneck in the development of integrated circuits, one of the most expensive and problematic parts of the design cycle. [0003] The test cost is related to many factors, among which the increasing huge amount of test data is one of the important factors related to the test cost. The test data is inc...

AI Technical Summary

Problems solved by technology

The test data is increasing exponentially year by year, and the amount of test data will reach 120Gb by 2014. Such a large amount of data has caused the following problems: (1) The bandwidth between the hard disk and the automatic test equipment (Automatic Test Equipment, ATE) is limited, making the test data The time to transfer from the hard disk to ATE is longer than the time to transfer test data from ATE to the circuit under test (CUT), which will result in a longer time wasted waiting for the loading of test data from the hard disk to ATE

(2) The limited storage capacity of ATE makes it necessary to cut or load test data in batches

If the test data is cut, the test quality will be reduced; if the test data is loaded in batches, the test time will be increased

(3) The bandwidth between ATE and CUT is limited, so that the loading time of test data from ATE memory to CUT cannot be reduced

In addition, due to the different sensitization paths, several test vectors may be generated for the same fault point, and some of these test vectors may be more easily embedded in the previous fold set

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