A method for quickly judging the test results of a SOC chip

Abstract

The invention discloses a method for quickly judging the test results of an SOC chip, which is realized by adding a DFT circuit in the original design of the chip. The method uses the memory unit of the chip itself to store the test information of the chip. After the chip is packaged, the test information needs to be read , follow the steps below: (1) power on the chip; (2) input the mode signal, enter the test information code operation mode, and select the storage unit for storing the test information; (3) input the clock signal; (4) input the test Vector, read test information; (5) output pulse. The method is convenient and fast, can not only improve the efficiency of chip analysis and testing, but also reduce the cost of analysis and testing. When using this method to read the test information of the chip, as long as the corresponding test vector is printed on the pin of the chip under test, the I / O port of the chip will output the pulse signal corresponding to the test information. The relevant test information can be judged conveniently.

Description

technical field [0001] The invention relates to a method for quickly judging the test result of an SOC chip. Background technique [0002] SOC (System on Chip, system-on-chip) is a system-level VLSI that integrates a CPU, various memories, bus systems, dedicated modules, and various I / O interfaces in the same chip. With the development of semiconductor process technology, the proportion of SOC in integrated circuit products is increasing, and the output value is also increasing. Due to the high integration and complexity of SOC circuits, the difficulty and cost of analysis and testing of SOC finished products are also higher than those of general integrated circuit chips. If it is possible to easily obtain the test information of SOC at various stages such as CP (Circuit probing) test and FT (Final test) test when performing subsequent analysis work such as Wafer (wafer) abnormality retest or chip failure analysis, there will undoubtedly be It helps to simplify the analysi...

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Problems solved by technology

However, the Mapping diagram can only record the CP test information of the chip, and does not involve the FT test stage. Moreover, once the chip is cut from the wafer and loses its position coordinates, it is difficult to judge the CP test result of the chip based on the Mapping diagram.

Another method is that the wafer manufacturer writes the test information into the chip after the chip is tested. When it is necessary to know the test information in the future, it can obtain the test information by reading the information of the chip. However, generally speaking, after the chip is packaged Or according to the needs of confidentiality, after the test is completed, the test interface will be automatically closed because some pads (pins) are packaged or the test channel is cut, so that the test information can no longer be read directly, but only by patching the pad, etc. To obtain, not only troublesome, but also very expensive

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