Electrostatic protection structure

Abstract

The invention provides an electrostatic protection structure. The electrostatic protection structure consists of an N-channel metal-oxide semiconductor (NMOS) transistor, a resistor and a pressure welding pad, wherein the gate end, a P-type substrate and a source end of the NMOS transistor are connected and are grounded; the drain end is connected with the pressure welding pad; one end of the resistor is connected with the pressure welding pad; the other end is the output end of the electrostatic protection structure and is connected with an internal circuit of a chip; the NMOS transistor also comprises an N-type diffusion area, polysilicon, a source-end substrate leading-out wire and an isolation ring; the overlapping part of the polysilicon and the N-type diffusion area forms the gate end; the N-type diffusion area comprises N-traps on the P-type substrate; the source end and the drain end are both formed by the N-traps and are in interdigital crisscross distribution; through holes are reserved in the N-traps in which the source end and the drain end are positioned; the through hole of the source end is connected with the source-end substrate leading-out wire; the isolation ring is connected with the source end; the source-end substrate leading-out wire is also connected with the P-type substrate; the resistor is formed by the polysilicon; and the polysilicon is directly connected with the pressure welding pad. The electrostatic protection structure can greatly improve electrostatic discharge (ESD) capacity, shorten chip area and reduce chip cost, and does not influence chip performance without changing process conditions.

Description

technical field [0001] The present invention relates to an integrated circuit, in particular to an electrostatic protection structure of a chip, and is particularly suitable for saving chip area. Background technique [0002] With the rapid development of integrated circuits, the issue of how to control costs has also been put on the table. For designers, the control of chip area is the most prioritized and effective method. And people's requirements for chips are getting higher and higher. In the application process of the chip, people hope that the function of the chip is not only correct, but also improves the performance requirements of the chip. [0003] Electrostatic discharge (ESD, Electrostatic Discharge) is a major factor that causes electronic components or electronic systems to be damaged by excessive electrical stress (Electrical Over Stress, EOS). Among the various means of electrostatic protection, the most important and most effective way is to integrate the...

AI Technical Summary

Problems solved by technology

Since this structure needs to withstand a large current during ESD, it generally occupies a large proportion of the chip area, resulting in an increase in chip cost

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