Broadband read-write memory apparatus

Abstract

The invention belongs to the field of designing of integrated circuits and provides a read-write bandwidth improvement memory apparatus. Particularly, a broadband data read-write port, besides a normal read-write port, is arranged on a memory in four modes, namely a wide bandwidth read mode, a normal bandwidth read mode, a wide bandwidth write mode and a normal bandwidth write mode. Different columns of memory units, which share word lines, of a memory array can pass through a broadband data write-in port and perform write-in operation simultaneously; and after values in the memory units corresponding to an input address is read out during read-out, values inside all other columns of memory units which share the word lines can be read out through a broadband data read-out port. Write-after-read operation can be performed on different memory rows of the memory array in the same clock period. A plurality of memory arrays can share a group of read-out apparatuses, and read-write operation in different arrays can be performed simultaneously.

Description

technical field [0001] The invention relates to the field of integrated circuit design, and relates to a method and a device for improving memory read and write bandwidth through structure optimization. Background technique [0002] With the advancement of technology and the increase of actual demand, in the field of storage circuit design, the scale of memory arrays is getting larger and larger. Usually, the physical layout of the memory array is rectangular, and the layout area of ​​the readout device occupies a considerable part of the chip area of ​​the entire memory. Logically, memory cells in several different columns usually share a word line. Traditional memory read and write methods write or read a set of data for each clock cycle. Taking a 512X32-bit single-port static random access memory (SRAM) array as an example, the SRAM array at the physical level is usually designed as 128 rows, and each row has 4X32 SRAM cells. Group readout device. [0003] When writing...

AI Technical Summary

Problems solved by technology

For multi-port SRAM memory, multiple read and write operations can be completed in one clock cycle, but at the expense of increasing the number of SRAM cell word lines and bit lines, SRAM cell layout area, control complexity, design and manufacturing costs

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