Method and system for realizing bus connection

Abstract

The invention discloses a method and a system for realizing bus connection. The method comprises the following steps that: a main module buffer receives a transmission request, initiated by a main module, of an advanced expandable interface bus; the main module buffer writes information according to the transmission request; when the main module buffer has the information, the main module buffer transmits the information to a slave module buffer; and the information is transmitted buffer to a slave module by the slave module. By the method and the system for realizing the bus connection, which is provided by the invention, as the main module buffer and the slave module buffer are adopted between the main module and the slave module, the signal input / output between the main module and the slave module is connected with a register, and the time sequence optimization of the bus connection can be guaranteed to the maximum extent.

Description

technical field [0001] The invention relates to a method and system for realizing bus connection. Background technique [0002] With the development of integration technology and the continuous expansion of application fields, different types of integrated circuits are embedded with each other, forming various embedded systems (Embedded System, ES) and systems on a chip (System On Chip, SOC). Among them, SOC refers to the technology of integrating a complete system on a single chip and grouping all or part of the necessary electronic circuits. The so-called complete system generally includes a central processing unit (CPU), memory, and peripheral circuits. [0003] The interconnection between SOCs also has relatively high requirements for the bus. Since the Advanced eXtensible Interface (AXI) bus is an advanced bus interconnection technology with very high efficiency of separating read and write, and separating addresses and data, therefore, Generally, the interconnection ...

AI Technical Summary

Problems solved by technology

However, sometimes it is necessary to use an AXI bus to connect between chips or between a chip and a field-programmable gate array (Field-Programmable Gate Array, FPGA). The delay of the PAD itself is relatively large. In this case, when the AXI bus is used to connect, the operating frequency cannot be very high, and the timing cannot meet the requirements of high-frequency operation.

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