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NAND flash controller circuit of multi-channel shared data cache region

A data cache area and data sharing technology, which is applied in the direction of digital memory information, static memory, instruments, etc., can solve the problem of large area

Active Publication Date: 2011-06-15
SHANGHAI HUAHONG INTEGRATED CIRCUIT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This kind of controller chip has a larger area

Method used

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  • NAND flash controller circuit of multi-channel shared data cache region
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  • NAND flash controller circuit of multi-channel shared data cache region

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Experimental program
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Embodiment Construction

[0028] specific implementation plan

[0029] According to the solution provided by the present invention, select the best embodiment in conjunction with each accompanying drawing and describe the implementation of the content of the invention:

[0030] (1) The size of the single-channel buffer area when the data buffer area is exclusive

[0031] When each channel exclusively shares the data buffer area, the size of each channel's data buffer area is determined by the data storage strategy on the NAND flash. The storage strategy of data on NAND flash refers to how the system allocates data with continuous logical addresses to different NAND flashes. Data can be stored in blocks, pages, sectors or other sizes. exist on different NANDflash. The size of each channel data buffer is usually the size of a data unit. In the embodiment of the present invention, the data unit is a sector with a size of 512 bytes.

[0032] (2) Shared data buffer area, data buffer address list, buffer...

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PUM

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Abstract

The invention provides a NAND flash controller circuit of a multi-channel shared data cache region. The NAND flash controller circuit comprises a main controller, a shared data cache region unit and a NAND flash interface control logic unit, wherein the shared data cache region unit consists of a data cache region, a data cache region address list and a data cache region address first-in first-out (FIFO) unit which are realized by adopting a flip-flop, a latch, a static random access memory (SRAM) or an off-chip synchronous dynamic random access memory (SDRAM) and a double data rate synchronous dynamic random access memory (DDRSDRAM). By adoption of the shared data cache region, the capacity of the data cache region of a multi-channel NAND flash controller is reduced, the design area of the controller chip is reduced effectively, the data transmission time is guaranteed, and the application requirement is met.

Description

technical field [0001] The invention relates to a large-capacity NANDA flash controller circuit, in particular to a NAND flash controller circuit with multiple channels sharing a data buffer area. technical background [0002] NAND flash has developed by leaps and bounds in recent years, from 1-bit / unit SLC single-level storage (Single Level Cell) technology to 2-bit / unit or even 3-bit / unit MLC multi-level storage (Multi Level Cell) Cell) technology, while the production process of NAND flash is also constantly improving. With the development of technology, the capacity of NAND flash continues to increase, and the cost per unit capacity is also greatly reduced. Compared with magnetic storage media, NAND flash has the advantages of power saving and short seek time, so it is regarded as the best choice to replace the existing magnetic storage media. NAND flash is currently mainly used in U disk, MP3, MP4, digital cameras and other fields. The data transmission bandwidth requ...

Claims

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Application Information

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IPC IPC(8): G11C11/413
Inventor 迟志刚
Owner SHANGHAI HUAHONG INTEGRATED CIRCUIT
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