Apparatus and method for correcting duty cycle of clock signal

Abstract

A clock correction circuit includes a delay locked loop (DLL) configured to delay an external clock signal and to generate an internal clock signal, a first duty cycle correction (DCC) unit configured to correct a duty cycle of the external clock signal in response to a first duty cycle code, a second DCC unit configured to correct a duty cycle of the internal clock signal in response to a second duty cycle code, and a duty cycle code generation unit configured to select an output of from outputs of the first and second DCC Units and to generate the first and second duty cycle codes by detecting a duty cycle ratio of the selected output.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2009-0104624 filed on October 30, 2009, the entire contents of which are incorporated herein by reference. Background technique [0003] Exemplary embodiments of the present invention relate to an apparatus for correcting a duty cycle of a clock signal. [0004] Clock signals are widely used in various systems and circuits to adjust the timing of operations. When clock signals are used inside systems and circuits, clock signals are often delayed. To ensure reliable operation, it is important to correct for delays. Typically a delay locked loop (DLL) is used to compensate for the delay of the clock signal. [0005] figure 1 is a block diagram showing a legacy DLL. [0006] The conventional DLL 100 includes a phase comparison unit 110 , a delay control unit 120 , a variable delay unit 130 , a replica delay unit 140 and a lock detection unit 150 . ...

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Problems solved by technology

However, the change in duty cycle caused by the variable delay unit 130 is not corrected for

Meanwhile, if the DCC circuit 200 is coupled to the output terminal of the DLL, a change in the duty ratio caused by the variable delay unit 130 can be corrected, but the duty ratio of the external clock EXTCLK input to the DLL is not corrected, and therefore, from The internal clock signal output by the DLL has an imprecise duty cycle

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