Access control method of synchronous dynamic memory

Abstract

The invention provides a high-efficiency access control method of a synchronous dynamic memory. By using a Round robin scheduling algorithm improved by combining a port grouping arbitration mechanism, a Bank internal arbitration mechanism and a Bank intermediate arbitration mechanism, a high-efficiency disorder scheduling algorithm, a weighting system arbitration algorithm and other technical means to realize the high-efficiency access and save sequence, the invention not only retains the advantages of two universal operation sequences, but also avoids the defects of the two operation time sequences and overcomes the defect that an FIFO (First In First Out) cache request mechanism requires to be configured with greater FIFO. According to the method, the requirement for high-efficiency data interaction under various conditions can be met by using smaller cache space.

Description

[0001] Field [0002] The invention relates to a memory control method, in particular to an efficient synchronous dynamic memory (SDRAM) memory access control method. technical background [0003] As the speed gap between the memory and the processor increases, the bandwidth of the memory cannot meet the data requirements of the processor. DRAM DRAM from SDR SDRAM to DDR SDRAM, and then to the current mainstream DDR2 SDRAM and DDR3 SDRAM, the frequency is constantly increasing, but the increase in frequency brings greater challenges to circuit design, while the read and write of SDRAM controller Efficiency also puts forward higher and higher requirements. Conventional SDRAM controller design methods have been unable to meet the bandwidth requirements of increasingly complex systems. [0004] The basic operation timing sequence for most existing SDRAM controllers to read and write external SDRAM is: [0005] 1) Operate the same row in the same logical bank: the situation whe...

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Problems solved by technology

[0005] 1) Operate the same row in the same logical bank: the situation when operating according to the JEDEC specification conventional memory access sequence is as follows figure 1 As shown, when tRCD=4, tRP=4, CL=4, tRAS=15, tRC=19, tRRD=4, tCCD=2, BL=4, the line from activation (Active) to precharge (Precharge) at least It needs 15T (T is the clock cycle). When operating on the same row continuously, the time for waiting is less, and the bus utilization rate will be higher. When the length of continuous operation on the same row is small, it needs to be precharged before switching rows (Precharge) The current working line needs to waste a lot of invalid waiting time, and the effective utilization rate of the bus is very low

[0006] 2) Interleave operation between different logical banks, also known as ping-pong operation: perform interleave operation among multiple banks according to the IDD7 memory access sequence in the JEDEC specification, and use Auto Precharge operation to hide the Precharge cycle, such as figure 2 As shown, when tRCD=4, tRP=4, CL=4, tRAS=15, tRC=19, tRRD=4, tCCD=2, BL=4, it can be seen from the figure that due to the use of the Auto Precharge command , at the same time as sending the row operation, issue a charge command to close the operation row, which hides the charging cycle. At the same time, this sequence also uses the new technology Posted CAS of DDR2, that is, after sending the Active command, the column operation command is sent immediately, but due to tRRD is at least 4T, so there is still a waiting time between two Bank activations, and the bus utilization in this case is only about 50%

[0008] Existing solutions solve the shortcomings of conventional sequences to a certain extent, but the use of Bank rotation combined with Auto Precharge has a large dependence on requests, and the efficiency is still low when the row hit requests are scattered.

However, the use of FIFO cache memory access sequence needs to configure a large FIFO, which not only improves the efficiency, but also greatly increases the delay of memory access, and also increases the cost.

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