Clock delay compensation device and clock delay compensation synchronization method

Abstract

The invention relates to a clock delay compensation device which comprises a first trigger circuit, a delay compensation circuit, a second trigger circuit, a crystal oscillator and a time output circuit. The crystal oscillator is connected with the time output circuit and the delay compensation circuit respectively; the delay compensation circuit is also connected with the first trigger circuit and the second trigger circuit respectively; the second trigger circuit is also connected with the time output circuit; and the crystal oscillator is used for providing stable clock frequency for the time output circuit and the delay compensation circuit. Moreover, the invention also provides a clock delay compensation synchronization method for realizing clock synchronization by using the clock delay compensation device. By means of the technical scheme, the the clock synchronization precision cane be improved and the invention is applicable to occasions with relatively high requirements on clock accuracy such as nuclear power, high-speed rails, stations and airports.

Description

technical field [0001] The invention relates to the field of clock synchronization in master and master clock systems, in particular to a device capable of realizing clock delay compensation and a clock delay compensation synchronization method. Background technique [0002] The single-item comparison method is an important method for clock synchronization in the master clock system at present. The clock synchronization process is as follows: [0003] In the first step, at T 0 At the moment, the standard clock sends a clock synchronization signal to the calibrated clock through the communication system. In the second step, after the transmission delay d, the calibrated clock receives the above-mentioned clock synchronization signal, and records the received time stamp, wherein the actual time when the calibrated clock receives the clock synchronization signal is T 1 , but the time of record reception is T 2 , so a time stamp error t will be generated in this step. In the...

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Problems solved by technology

In the second step, after the transmission delay d, the calibrated clock receives the above-mentioned clock synchronization signal, and records the received time stamp, wherein the actual time when the calibrated clock receives the clock synchronization signal is T 1 , but the time of record reception is T 2 , so a time stamp error t will be generated in this step

The fourth step is to adjust the synchronization time T of the calibrated clock 3 = T 0 +d; Among them, the transmission delay d is known, but the time stamp error t and the signal processing time tˊ are difficult to measure and estimate, so the synchronization time accuracy obtained by this clock synchronization method is poor, see Figure 5

In this way, the error between the calibrated clock and the standard clock is relatively large, and it is not suitable for nuclear power, high-speed rail, stations, airports and other places that require high clock accuracy.

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