Network-on-chip oriented low delay router structure

Abstract

The invention discloses a network-on-chip oriented low delay router structure, aiming to solve the problems that the existing router structure has relative large delay in forwarding fragments and can not make full use of storage resources in physical links. The invention consists of P numbered input units, P numbered output units and P numbered channel double buffer; each input unit consists of a buffer distributor, an input buffer and p numbered virtual output address queues; each output unit consists of a P:1 arbiter and a P:1 selector; the channel double buffer consists of a controller and a double buffer; the controller consists of a read pointer, a write pointer and a state machine; and the double buffer consists of two registers and a selector. The fragment transmission between routers adopts a ready-effective synchronous handshake protocol. By adopting the invention, both the delay in forwarding the fragments and the design complexity are reduced, the storage resources in the physical links are fully utilized, and the use ratio of the buffer of the input unit is improved.

Description

technical field [0001] The invention relates to an on-chip router structure in the field of microprocessors, in particular to an interconnection structure between processor cores and high-speed buffer bodies in a chip multiprocessor (ChipMulitProcessor). Background technique [0002] With the proportional reduction of the size of CMOS integrated circuit technology, the number of processor cores integrated on a single chip has increased rapidly. Today, the number of processor cores in commercial processors has reached 16. When the number of processor cores is relatively small, you can use crossover Centralized interconnection structures such as switches. The scalability of the crossbar switch is relatively poor. When the number of processor cores reaches dozens or even hundreds, it is no longer suitable due to design complexity and area overhead. At the same time, interconnect delays increase relative to logic gate delays, increasing the design complexity of multi-core proce...

AI Technical Summary

Problems solved by technology

[0011] The technical problem to be solved by the present invention is to provide a network-on-chip router structure with dual clock cycles in view of the problems that the existing router structure has a large delay in forwarding packets and cannot fully utilize the storage resources in the physical link. Reduce the delay of forwarding packets, reduce the design complexity, and make full use of the storage resources in the physical link

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