Etch tank adopted in process of packaging and manufacturing TSV (Through Silicon Via) wafer and preparation process
A process method and etching groove technology, which are applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of reduced contact area, inability to realize wafer plating process, etc., to achieve thin thickness, improve yield, simple craftsmanship
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[0015] In order to fully demonstrate the advantages and positive effects of the present invention, the present invention will be further described below in conjunction with the accompanying drawings and embodiments.
[0016] exist figure 1 In this method, a layer of Au layer 102 with strong oxidation resistance is sputtered on one side of the supporting wafer 101 with a thickness of about 100-200 nm. The role of this metal layer is to provide a seed layer for TSV electroplating Cu. Then a layer of BCB 103 is coated on the metal layer 102, and the thickness of the BCB is about 2-4 μm. The BCB is shaped by photolithography, so that the BCB that will be bonded to the TSV position 104 is removed.
[0017] exist figure 2 Among them, using photoresist as a mask, DRIE is used to etch the etching groove 203 on the front side of the TSV wafer 201, the groove wall has a vertical feature, the depth of the etching groove is 2-3 μm, and the surface area is 1.2-1.3 times that of the BCB...
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