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Floating body cell structure of dynamic random access memory and manufacturing technology thereof

A memory cell, dynamic random technology, applied in static memory, semiconductor/solid-state device manufacturing, digital memory information, etc., can solve the problem of difficult control of leakage current characteristics, and achieve low leakage current, low manufacturing cost, and simple manufacturing process. Effect

Inactive Publication Date: 2010-07-07
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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Problems solved by technology

[0004] This 1T / FB unit structure reduces the unit area, and its unit area size is 4-7F 2 (F refers to the feature size), which greatly improves the integration of memory, but this kind of cell structure will increase the complexity of circuit and logic design, and its leakage current characteristics are also difficult to control

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  • Floating body cell structure of dynamic random access memory and manufacturing technology thereof
  • Floating body cell structure of dynamic random access memory and manufacturing technology thereof
  • Floating body cell structure of dynamic random access memory and manufacturing technology thereof

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Embodiment Construction

[0059] The device structure of the present invention will be further described below in conjunction with the accompanying drawings, which are not drawn to scale for the convenience of illustration.

[0060] Such as Figure 4 As shown, a cell structure of a high-efficiency, low-power, and highly integrated gate diode floating body DRAM based on the band-to-band tunnel penetration effect, which includes: a buried oxide layer (BOX) 100, located in the buried oxide layer The first N-type semiconductor region 201 on the 100, the P-type semiconductor region 203 positioned on the first N-type semiconductor region 201 and the gate region positioned on the P-type semiconductor region 203; one side of the P-type semiconductor region 203 is provided with The second N-type semiconductor region 202, and the second N-type semiconductor region 202 communicates with the first N-type semiconductor region 201; Shallow trench isolation regions 300 are arranged around the active region of the ac...

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Abstract

The invention discloses a floating body cell structure of a dynamic random access memory and manufacturing technology thereof. The structure comprises an N type semiconductor area on a buried oxide layer (BOX), a P type semiconductor area on the N type semiconductor area and a gate area on the P type semiconductor area. Electric isolation areas are arranged around the P type semiconductor area and the N type semiconductor area. In the invention, isolated floating body gate diodes are employed as the storage nodes. Through tunneling among bands, the state that holes are accumulated in the floating body is defined as the first storage state. Through forward bias of PN junctions, the state that the holes are transmitted from the floating body or the electrons are injected into the floating body is defied as the second storage state. The two states lead to difference of the forward turn-on voltage of the floating body gate diodes (P+ / N+) and can be sensed through the current intensity. The gate diode (P+ / N+) floating body cell of the memory has high efficiency, low power consumption and high density and has the advantages of simple manufacturing technology, high integration density, low cost, high reliability, etc.

Description

technical field [0001] The invention relates to a memory unit structure and a manufacturing process thereof, in particular to a dynamic random access memory (DRAM) unit structure utilizing a floating body effect (FBE, Floating Body Effect) and a manufacturing process thereof, belonging to the technical field of semiconductor manufacturing. Background technique [0002] With the development of VLSI technology, advanced technology enables people to integrate processors, memory, analog circuits, interface logic and even radio frequency circuits into a large-scale chip to form a so-called system on chip (SoC). As an important part of SoC, embedded memory and other logic circuits are integrated in one chip. At present, the proportion of the total chip area in microprocessors and system chips has exceeded 50%, and as the needs of applications will increase continue to grow. Following Moore's Law, the feature size of CMOS technology will continue to be scaled down to below 40nm, a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/108H01L21/8242
CPCG11C2211/4016H01L29/7841H01L27/10802G11C11/404H10B12/20
Inventor 肖德元王曦陈静
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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