Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Link layer controller of IEEE1394 bus

A technology of link layer and controller, which is applied in the direction of bus network, data exchange through path configuration, electrical components, etc. It can solve the problems that aerospace-grade devices are not easy to obtain, and achieve good versatility and high performance.

Inactive Publication Date: 2012-12-12
CENT FOR SPACE SCI & APPLIED RES
View PDF0 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Realized by using high-grade FPGA devices, or after tape-out of ASIC with radiation-resistant technology, the controller can be used in aerospace electronic equipment, solving the problem that aerospace-grade devices of IEEE1394 bus are not easy to obtain

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Link layer controller of IEEE1394 bus
  • Link layer controller of IEEE1394 bus
  • Link layer controller of IEEE1394 bus

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0040] The present invention will be described in detail below with reference to the drawings.

[0041] Such as figure 1 As shown, the present invention is composed of five basic modules: host interface, high-speed data interface, data buffer and routing, link layer core module and configuration register.

[0042] The host interface part provides a universal 16-bit CPU interface, through which timing coordination with different CPUs can be realized. The host interface module is internally connected to the configuration register, data buffer and routing control module through a 16-bit bidirectional data bus and some control lines. The external CPU can use this interface to read and write the configuration register inside the link layer controller, and access the data buffer: write the data packet to be sent or read the received data packet. The timing of the host interface is completed under the control of the clock signal provided by the external CPU. Therefore, the read and write...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a link layer controller of an IEEE1394 bus, which comprises a host computer interface, a link layer core module, a data buffering and routing control module, a high-speed data interface module and a configuration register, wherein an external CPU (central processing unit) can read and write data buffering areas in the configuration register and the access data buffering and routing control module by the host computer interface; the data buffering and routing control module is positioned among the link layer core module and the host computer interface and a high-speed data interface, used for providing the switching control among different data receiving and sending channels and also provided with two asynchronous first-in first-out memories which are respectively used for the buffering of receiving and sending data and the synchronization of cross-clock domain data; and the configuration register is used for providing initial configuration and control for the link layer core module and the data buffering and routing control module and controlling and acquiring the working states of all modules of the link layer controller by the host computer interface reading and writing configuration register, and has good portability.

Description

Technical field [0001] The present invention relates to the design of a computer standard serial bus-IEEE1394 bus protocol controller, in particular to a link layer controller of the IEEE1394 bus applied in the field of space electronics technology. Background technique [0002] In an electronic system, in order to simplify the hardware circuit design and optimize the system structure, a group of lines is commonly used, configured with appropriate interface circuits, and connected to various components and peripheral devices. This group of shared connection lines is called a bus. The use of a bus structure facilitates the expansion of components and equipment, especially the development of a unified bus standard, which makes it easier to interconnect different equipment. Advanced bus technology has a very important impact on improving the performance of electronic systems. [0003] In the early spacecraft, the bus structure was not used. The communication between the computer and ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H04L29/06H04L12/40
Inventor 周庆瑞孙辉先陈晓敏凡启飞曹松
Owner CENT FOR SPACE SCI & APPLIED RES
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products