Device for achieving LPC-USB two-way communication by using FPGA and data conversion method of LPC-US and USB-LPC

Abstract

The invention relates to a device for achieving LPC-USB two-way communication by using an FPGA and a data conversion method. The device comprises an LPC bus, a USB bus, a field programmable logic device and a USB module, wherein the field programmable logic device finishes the protocol conversion and transmission from LPC data to USB data from the LPC bus to the USB bus, and finishes the protocolconversion and transmission from the USB data to the LPC data from the USB bus to the LPC bus. The device achieves the full-duplex communication of the LPC bus and the USB bus by using the FPGA so asto satisfy certain special application occasions and solve the problems of the short-range communication of two or more computers without the help of other media. The device adopts a scheme with the FPGA and a USB control chip, and two FIFOs are arranged in the FPGA to replace an external FIFO so as to achieve high integration, and an integrated circuit board is manufactured to have the minimum area, the lowest power consumption and the least cost. Besides, the device uses the characteristic of occupying fewer ports of the FIFO to ensure that FIFO only occupies an address space of less than 2bits in a PC, thereby greatly saving the address space. Simultaneously, the device uses the characteristic of parallel high speed of the FPGA so that the scheme can satisfy the high-speed full-duplexcommunication.

Description

technical field [0001] The invention relates to a bidirectional communication device, more specifically, to a device using FPGA to realize LPC-USB bidirectional communication and a data conversion method between LPC-USB and USB-LPC. Background technique [0002] The low pin count (Low Pin Count, LPC) bus is a data address command multiplexing bus defined by Intel (Intel), which works at 33MHz (megahertz). In the computer field, the LPC bus has gradually replaced the Industry Standard Architecture (Industry Standard Architecture, ISA), X-bus (X-bus), etc., and has become a new interface. [0003] The LPC bus has the characteristics of serial and parallel, which not only has some characteristics of the serial bus, but also has some characteristics of the parallel bus. In the communication process, there are frame signals, synchronization signals, and response signals in the traditional serial communication protocol, but in the entire communication process, it is transmitted w...

AI Technical Summary

Problems solved by technology

[0007] 1. Use CPLD or FPGA with an external dual-port RAM+USB chip for full-duplex communication; its disadvantages: independent dual-port RAM is expensive; operating dual-port RAM is prone to competition problems, that is, the same Sometimes, both sides of the RAM write to the same address at the same time, and the data will be lost; the address space of the RAM must be mapped to the addressing space of the computer, the larger the capacity of the RAM, the larger the address space occupied; the data movement of the RAM, Software is required to do complex space management, and to implement different operations on data at different addresses, the technical implementation is complicated

[0008] 2. Use CPLD or FPGA alone, with 2 external FIFO chips + USB chip for full-duplex communication; its disadvantages: need to use 2 FIFO chips at the same time, which is expensive; need to use FPGA or CPLD to write FIFO interface The program communicates with the FIFO for data; 4 ICs are required, which increases the board area and power consumption

[0009] 3. FPGA embedded processor, such as (NIOS II, Microblaze), external single-port RAM+USB chip for communication; its disadvantages: first, the embedded processor requires a larger capacity FPGA, and the cost is not easy to grasp; because it is an internal Embedded processor, so only one port can be operated at a single time, so it can only be in half-duplex mode; because the data transmission rate is as high as 10MB / S, if the embedded processor is used, an external cache module must be installed. The soft processor with low performance will be the bottleneck of the data channel

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