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Resistive superconductive asynchronous bilinear logic universal gate circuit

A two-wire logic, resistive technology, applied in the direction of logic circuits with logic functions, etc., can solve the problems of difficult wiring, too many junctions, etc., and achieve the effect of simple and convenient wiring and small time delay.

Inactive Publication Date: 2011-07-20
HANGZHOU DIANZI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for the existing Josephson junction superconducting circuit manufacturing process, there are problems of too many junctions and difficult wiring.

Method used

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  • Resistive superconductive asynchronous bilinear logic universal gate circuit
  • Resistive superconductive asynchronous bilinear logic universal gate circuit
  • Resistive superconductive asynchronous bilinear logic universal gate circuit

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Embodiment Construction

[0023] The present invention will be further described below in conjunction with the accompanying drawings.

[0024] Such as figure 2 As shown, one end of the first connection inductance L1 in the present invention is the first input terminal A1, the other end of the first connection inductance L1 and one end of the second connection inductance L2 are connected to one end of the first Josephson junction J1, the first The other end of the Josephson junction J1 is grounded; the other end of the second connection inductor L2 and one end of the third connection inductor L3 are connected to the output end of the first current source I1, and the ground terminal of the first current source I1 is grounded; the third connection inductor The other end of L3 and one end of the first magnetic flux preservation inductance L24 are connected to one end of the second Josephson junction J2, and the other end of the second Josephson junction J2 is grounded; the other end of the first magnetic ...

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Abstract

The invention relates to a resistive superconductive asynchronous bilinear logic universal gate circuit. A logic gate structure of the prior superconductive asynchronous bilinear circuit has the defects of great amount of used Josephson junctions and difficult wiring. The resistive superconductive asynchronous bilinear logic universal gate circuit comprises four Josephson quantum interference devices and two choking resistors, and each Josephson quantum interference device comprises four Josephson junctions and three connecting inductors, wherein two adjacent Josephson quantum interference devices share two Josephson junctions. The logic gate structure proposed by the invention utilizes resistors to consume a loop current remained in the gate circuit after the logic gate is triggered so as to greatly reduce the number of the needed Josephson junctions. The invention is favorably compatible to the wiring convenience. Compared with the prior art, circuittopology in a sequential structure is easier to apply to a large-scale superconductive integrated circuit.

Description

technical field [0001] The invention belongs to the technical field of superconducting digital circuits, and relates to a resistive asynchronous dual-rail (Dual-Rail) logic general-purpose gate circuit structure used in superconducting RSFQ (Rapid Single Flux Quantum) digital integrated circuits. Use combiners to form AND gates, OR gates, and XOR gates. Background technique [0002] In 1985, K.K.Likharev, O.A.Mukhanov and V.K.Semenov proposed a logic circuit technology based on Josephson junctions, that is, superconducting fast single flux quantum (Rapid Single Flux Quantum) technology. [0003] A Josephson junction consists of a weak link (usually a tunnel junction) between two superconductors. The junction can switch between superconducting and normal states on the order of picoseconds. A concomitant single flux quantum voltage pulse is generated across the junction during the switching process. Fast single magnetic flux quantum digital circuit technology is to use sin...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/20
Inventor 官伯然王磊吴爱婷方志华张忠海
Owner HANGZHOU DIANZI UNIV
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