Memory circuit

Abstract

A memory circuit includes a bit line; a word line; a first power supply node having a first power supply voltage; a first power supply line connected to the first power supply node; a second power supply node selected from a group consisting of a floating node and a node having a second power supply voltage lower than the first power supply voltage; a second power supply line configured to switch connections between the first and the second power supply nodes; a write-assist-keeper (WAK) device coupling the first and the second power supply lines; and a static random access memory (SRAM) cell connected to the bit line, the word line and the second power supply line. The invention increases read voltage tolerance and write voltage tolerance, improves VCCMIN.

Description

technical field [0001] The present invention relates to memory arrays, in particular to static random access memory (Static Random Access Memory, SRAM) arrays. Background technique [0002] Static Random Access Memory (SRAM) is often used in integrated circuits. An important feature of the SRAM lattice is that it does not need to refresh the memory to maintain data. SRAM cells have several different transistors and are often named according to the number of transistors they have, for example: 6T SRAM with six transistors, 8T SRAM with eight transistors, and so on. Generally, the plurality of transistors function as data latches to store one bit. In addition, other transistors can be added on it to control its access. The plurality of SRAM cells are usually arranged in an array with rows and columns. Each row of the plurality of SRAM cells is connected to a word line, and the word line determines which SRAM cell will be selected. Each column of the plurality of SRAM cell...

AI Technical Summary

Problems solved by technology

The same problem occurs even in single-supply architectures operating below 1 volt

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