CMOS device metal grid and method for forming same

Abstract

The invention provides a metal grid electrode of a CMOS element and a forming method thereof. With the technical proposal, the change of the thickness of the metal grid electrode can lead to obvious change of an effective work function value of the metal grid electrode material on the same high k (dielectric constant) grid medium, thus realizing the regulation of the effective work function value in simple and effective ways and further effectively regulating a threshold voltage of the high k grid medium / a CMOS element of a metal grid electrode structure. Therefore, the high k grid medium / the CMOS element of the metal grid electrode structure meeting the threshold voltage demands of a nano CMOS element can be obtained. Moreover, the adoption of the technical proposal can simplify the processing flow of the high k grid medium / the CMOS element of the metal grid electrode structure, thus not only reducing the deposition process of a double metal grid thin film, but also overcoming complex pattern etching problems of a double metal grid structure.

Description

technical field [0001] The present invention relates to the field of CMOS (Complementary Metal Oxide Semiconductor) devices in microelectronics technology, and more particularly relates to a metal gate of a CMOS device and a method for forming the same. Background technique [0002] With the rapid development of microelectronics technology, CMOS technology, the core of microelectronics technology, has become the supporting technology in modern electronic products. For decades, logic chipmakers have used silicon dioxide (SiO 2 ) as the gate dielectric and heavily doped polysilicon (poly-Si) as the gate electrode material. This combination continued into the 90nm technology generation. SiO in CMOS transistors as feature sizes continue to shrink 2 The size of the gate dielectric is approaching the limit, for example, in the 65nm process, SiO 2 The thickness of the gate has been reduced to 1.2 nanometers, which is about 5 silicon atomic layers thick. If it is further reduced...

AI Technical Summary

Problems solved by technology

However, the current method of adjusting the effective work function through these process factors is not effective, and the process is complicated, so the formed CMOS devices cannot meet the threshold voltage requirements of nano-CMOS devices

Images