Method for constructing network on three-dimensional chip

Abstract

The invention provides a three-dimensional network on chip (NoC) structuring method by using a horizontal-plane network structure and a flexible imaginary-plane network structure, wherein, the horizontal-plane network of which the network topology adopts a De Bruijn picture is a plane extending along the X direction and the Y direction; while the imaginary-plane network is a curved surface extending along the three directions of X, Y and Z, the network can be formed by connecting certain nodes of each layer of the horizontal-plane network according to the requirement for solving certain problems such as reducing the wiring complexity or improving the fault-tolerant character, namely, the nodes are not necessarily in a vertical plane. The invention also provides two kinds of imaginary-plane structuring methods comprising a De Bruijn picture structure and a double-ring structure. The first method fully utilizing that the De Bruijn picture allows shorter routing algorithm reduces average hop times in the data transmission, provides a small network delay and has a better fault-tolerant character; the second method improves the transmission efficiency by using the characteristics of low wiring complexity of a ring structure and high data transmission speed and by combining the horizontal-plane network utilizing the advantage of small network diameter of the De Bruijn picture.

Description

technical field [0001] The invention belongs to a network connection method between processing units in an integrated circuit chip, in particular the connection of a three-dimensional on-chip network and the related data transmission process. Background technique [0002] In recent years, with the development of technology, a new form of packaging has emerged—three-dimensional packaging, that is, multiple bare chips are stacked vertically and packaged into a chip. The chip obtained by three-dimensional packaging is called a three-dimensional IC. Compared with the traditional two-dimensional IC, it has many advantages such as large capacity and high density. [0003] Because the architecture of the 3D NoC (Network on Chip) has a great influence on the network throughput, reliability, task mapping of the application layer, and the area and power consumption of the chip, the architecture of the 3D NoC is the most basic solution for realizing the 3D NoC. , the most important li...

AI Technical Summary

Problems solved by technology

[0013] Aiming at the problems of large network delay and low throughput in the existing architecture, the present invention provides a network structure based on De Bruijn graphs, breaks the traditional three-dimensional network of horizontal plane network and vertical plane decomposition, and proposes horizontal plane network and virtual Network-on-a-Chip Architecture Method for 3D Network Connections Composed of Planes

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