Asynchronous data triggering micro-processor architecture

Abstract

The invention relates to a system structure of an asynchronous data triggered microprocessor, which consists of a data path and a control path; the data path consists of a register file and a functional unit, wherein, the functional unit is connected with a data storage device for carrying out reading and writing on the data storage device; the control path comprises an instruction fetching unit and a coding unit; wherein, the instruction fetching unit is connected with an instruction storage device for reading the instruction from the instruction storage device; meanwhile, the instruction fetching unit is also connected with the coding unit for sending the instruction obtained to the coding unit to carry out coding; the control path and the data path are connected by an interconnecting network, and the coding unit sends the instruction coding result to the needed functional unit by the interconnecting network. The invention combines a plurality of design methods of the microprocessors with the design technologies thereof, which has simpler structure and higher performance; low power consumption of the microprocessors can be realized on the two aspects of the system structure and the circuit in the invention, therefore, the technology of a custom instruction set processor does not need to excessively consider numerous problems which are originally faced.

Description

technical field [0001] The invention belongs to the microprocessor architecture in the field of integrated circuits, in particular to an asynchronous data trigger microprocessor architecture. Background technique [0002] With the development of integrated circuit manufacturing technology, processors used in embedded systems need to meet the requirements of real-time, low power consumption, low cost and short time to market. Application Specific Integrated Circuits (Application Specific Integrated Circuits, ASIC) and general-purpose digital signal processors (Digital Signal Processor, DSP) are two traditional methods for completing embedded applications. The ASIC method provides customized data paths and control paths, with low power consumption and fast speed, but the use area is narrow, and at the same time, due to the small market capacity, the design cost of a single product is relatively high; and the versatility of DSP limits its development. Parallelism in a specific...

AI Technical Summary

Problems solved by technology

[0006] In the field of integrated circuit design, synchronous circuit design methods have always occupied the mainstream position. However, as the semiconductor process enters the deep submicron stage, the design of high-speed synchronous circuits has encountered unprecedented challenges. The design of the clock distribution network and the resulting functions Consumption, area occupation, clock distortion and other issues are becoming more and more prominent

For example, in DEC's Alpha processor, the clock network consumes about 30% of the power consumption and occupies about 30% of the entire chip area.

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