Pll circuit

Abstract

A PLL circuit includes a voltage-controlled oscillator (4), which has two voltage / current converting circuits (40,41) and a selecting circuit (42) for selecting an output of one of those voltage / current converting circuits (40,41). The output of the voltage / current converting circuit selected by the selecting circuit (42) is inputted to a current-controlled oscillator (45). The input side of the voltage / current converting circuit (41) is connected to the output side of a loop filter (3), while the input side of the other voltage / current converting circuit (40) is connected to an input terminal (8) used for evaluating the oscillation characteristic of the voltage-controlled oscillator (4). It is, therefore, achieved to effectively suppress both the temporal variation in output frequency ofthe PLL circuit and the temporal variation in voltage of the loop filter that would otherwise occur due to an arrangement in which the input terminal used for evaluating the oscillation characteristic of the voltage-controlled oscillator is connected to the loop filter via a switch.

Description

technical field [0001] The present invention relates to a PLL circuit (phase synchronization circuit) having a function of evaluating oscillation characteristics of a voltage-controlled oscillator. Background technique [0002] exist Figure 11 A conventional configuration diagram of a PLL circuit having an evaluation circuit of an oscillation characteristic of a voltage controlled oscillator (hereinafter referred to as VCO) is shown in . [0003] exist Figure 11 Among them, 1 is a phase comparator, 2 is a charge pump (charge pump) circuit, 3 is a loop filter, 4 is a voltage control oscillator (hereinafter referred to as VCO), 5 is a frequency division circuit, and 7 is a test control signal , 64, 65 are the switches controlled by the test control signal 7, 6 is the input signal, and 8 is the input control terminal of the VCO. A PLL circuit is formed by connecting a phase comparator 1, a charge pump circuit 2, a loop filter 3, a VCO 4, and a frequency dividing circuit 5 in...

AI Technical Summary

Problems solved by technology

[0009] However, in the above-mentioned conventional PLL circuit, in the locked state in which the output frequency of the output of the PLL circuit is substantially constant, the output portion of the loop filter 3 is in a high impedance state, and since the selection switch 64 is connected to this The output portion of the loop filter 3 in the high impedance state, therefore, it is judged that there is a problem that a weak current leaks from the output portion of the loop filter 3 in the high impedance state through the switch 64, and the weak leakage The output voltage of the above-mentioned loop filter 3 (the voltage of the input 67 of VCO4) changes due to the current, and the output frequency of the PLL circuit also changes with this change, and the output frequency cannot be controlled at a constant value with high precision.

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