Output circuit for FPGA clock signal and processing method thereof

Abstract

The invention discloses an FPGA clock signal output circuit, comprising a clock management unit and a global buffer, wherein a clock signal generated by the clock management unit is distributed by the global buffer; moreover, the FPGA clock signal output circuit also comprises a trigger unit and a selector, the end of the clock signal of the trigger unit is connected with the output end of the global buffer, a data input signal of the trigger unit is a constant logic signal, the trigger unit provides a positive output signal and a negative output signal to the end of the input signal of the selector, the control input end of the selector is connected with the end of the clock signal outputted by the clock management unit, and the selector outputs the clock signal to an output pin of the FPGA. The FPGA clock signal outputted by the circuit reduces the delay, and lowers the negative influence of the external load on an internal clock tree of the FPGA.

Description

technical field [0001] The invention relates to an FPGA clock signal output circuit. Background technique [0002] In modern integrated circuit design, the use of FPGA is becoming more and more common, especially in the field of ASIC design and application. FPGA can not only complete the prototype verification in the ASIC design process, but also directly play the role of ASIC in the relatively simple ASIC design. [0003] For the FPGA system, whether it is used for prototype verification or directly used as an ASIC, it is often necessary to output clock signals to peripheral devices, such as SDRAM clocks, LCD clocks, and camera clocks. However, due to the particularity of the FPGA production process, the wiring between the internal components has been completely fixed before leaving the factory, and the clock tree structure has been pre-cured in the FPGA chip; Therefore, FPGA cannot solve the clock skew problem by dynamically building a clock buffer tree like ASIC. In add...

AI Technical Summary

Problems solved by technology

In such a processing circuit and method, the clock signal output by the BUFG not only enters the clock terminal of the flip-flop, but also passes through the common logic unit. Therefore, the clock tree after the BUFG has a relatively large delay; moreover, the output clock signal The pointed peripheral load may reversely affect other clock signals on the clock tree through the output circuit of the two-stage inverting gate, causing phase shift and amplitude change of other signals. In severe cases, the entire FPGA clock the collapse of the tree

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